7.3.8.1 ADC, Mono, 48 kHz, DVDD = 1.8 V, AVDD = 3.3 V

AOSR = 128, Processing Block = PRB_R4 (Decimation Filter A)

Power consumption = 9.01 mW

AOSR = 64, Processing Block = PRB_R11 (Decimation Filter B)

Power consumption = 7.99 mW

7.3.8.2 ADC, Mono, 8 kHz, DVDD = 1.8 V, AVDD = 3.3 V

AOSR = 128, Processing Block = PRB_R4 (Decimation Filter A)

Power consumption = 6.77 mW

AOSR = 64, Processing Block = PRB_R11 (Decimation Filter B)

Power consumption = 6.61 mW

7.3.8.3 DAC Playback on Headphones, Stereo, 48 kHz, DVDD = 1.8 V, AVDD = 3.3 V,
HPVDD = 3.3 V

DOSR = 128, Processing Block = PRB_P7 (Interpolation Filter B)

Power consumption = 24.28 mW

DOSR = 64, Processing Block = PRB_P7 (Interpolation Filter B)

Power consumption = 24.5 mW

7.3.8.4 DAC Playback on Headphones, Mono, 48 kHz, DVDD = 1.8 V, AVDD = 3.3 V,
HPVDD = 3.3 V

DOSR = 128, Processing Block = PRB_P12 (Interpolation Filter B)

Power consumption = 15.4 mW

DOSR = 64, Processing Block = PRB_P12 (Interpolation Filter B)

Power consumption = 15.54 mW

7.3.8.5 DAC Playback on Headphones, Stereo, 8 kHz, DVDD = 1.8 V, AVDD = 3.3 V,
HPVDD = 3.3 V

DOSR = 768, Processing Block = PRB_P7 (Interpolation Filter B)

Power consumption = 22.44 mW

DOSR = 384, Processing Block = PRB_P7 (Interpolation Filter B)

Power consumption = 22.83 mW

7.3.8.6 DAC Playback on Headphones, Mono, 8 kHz, DVDD = 1.8 V, AVDD = 3.3 V,
HPVDD = 3.3 V

DOSR = 768, Processing Block = PRB_P12 (Interpolation Filter B)

Power consumption = 14.49 mW

DOSR = 384, Processing Block = PRB_P12 (Interpolation Filter B)

Power consumption = 14.42 mW

7.3.8.7 DAC Playback on Headphones, Stereo, 192 kHz, DVDD = 1.8 V, AVDD = 3.3 V,
HPVDD = 3.3 V

DOSR = 32, Processing Block = PRB_P17 (Interpolation Filter C)

Power consumption = 27.05 mW

7.3.8.8 DAC Playback on Line Out (10 k-Ω load), Stereo, 48 kHz, DVDD = 1.8 V, AVDD = 3 V,
HPVDD = 3 V

DOSR = 64, Processing Block = PRB_P7 (Interpolation Filter B)

Power consumption = 12.85 mW

7.3.9.1 MICBIAS and Microphone Preamplifier

The TLV320AIC3110 device includes a microphone bias circuit that sources up to 4 mA of current and is programmable to a 2-V, 2.5-V, or AVDD level. The level is controlled by writing to page 1 / register 46, bits D1–D0. Table 7-14 lists this functionality.

During normal operation, MICBIAS can be set to 2.5 V for better performance. However, based on the model of the selected microphone, optimal performance can be obtained at another setting and therefore the performance at a given setting must be verified.

The lowest current consumption occurs when MICBIAS is powered down. The next-lowest current consumption occurs when MICBIAS is set at AVDD.

Because of the oversampling nature of the audio ADC and the integrated digital-decimation filtering, requirements for analog anti-aliasing filtering are very relaxed. The TLV320AIC3110 device integrates a second-order analog anti-aliasing filter with 20-dB attenuation at 1 MHz. This filter, combined with the digital decimal filter, provides sufficient anti-aliasing filtering without requiring any external components.

The MIC PGA supports analog gain control from 0 dB to 59.5 dB in steps of 0.5 dB. These gain levels are controlled by writing to page 1 / register 47, bits D6–D0. The PGA gain changes are implemented with internal soft-stepping. This soft-stepping ensures that volume-control changes occur smoothly with no audible artifacts. On reset, the MIC PGA gain defaults to a mute condition, with soft-stepping enabled. The ADC soft-stepping control is enabled or disabled by writing to page 0 / register 81, bits D1–D0. ADC soft-stepping timing is provided by the internal oscillator and internal divider logic block.

The input feed-forward resistance for the MIC1LP input of the microphone PGA stage has three settings, 10 kΩ, 20 kΩ, and 40 kΩ, which are controlled by writing to page 1 / register 48, bits D7 and D6. The input feed-forward resistance value selected affects the gain of the microphone PGA. The ADC PGA gain for the MIC1LP input depends on the setting of page1 / register 48 and page 1 / register 49, bits D7–D6. If D7–D6 are set to 01, then the ADC PGA has 6 dB more gain with respect to the value programmed using page 1 / register 47. If D7–D6 are set to 10, then the ADC PGA has the same gain as programmed using page 1 / register 47. If D7–D6 are set to 11, then the ADC PGA has 6 dB less gain with respect to the value programmed using page 1 / register 47. The same gain scaling is also valid for the MIC1RP and MIC1LM input, based on the feed-forward resistance selected using page 1 / register 48, bits D5–D2.

Table 7-15 lists the effective gain applied by the PGA.

The MIC PGA gain is either controlled by an AGC loop or as a fixed gain. See for the various analog input routings to the MIC PGA that are supported in the single-ended and differential configurations. The AGC is enabled by writing to page 0 / register 86, bit D7. If the AGC is not enabled, then setting a fixed gain occurs by writing to page 1 / register 47, bits D6–D0. Because the TLV320AIC3110 device supports soft-stepping gain changes, a read-only flag on page 0 / register 36, bit D7 is set whenever the gain applied by PGA equals the desired value set by the gain register. The MIC PGA is enabled by writing to page 1 / register 47, bit D7. ADC muting occurs by writing to page 0 / register 82, bit D7 and page 1 / register 47, bit D7. Disabling the MIC PGA sets the gain to 0 dB. Muting the ADC causes the digital output to mute so that the output value remains fixed. When soft-stepping is enabled, the CODEC_CLKIN signal must stay active until after the ADC power-down register is written, in order to ensure that soft-stepping to mute has had time to complete. When the ADC POWER UP flag is no longer set, the CODEC_CLKIN signal can shut down.

7.3.9.2 Automatic Gain Control (AGC)

The TLV320AIC3110 includes automatic gain control (AGC) for the microphone inputs. AGC can be used to maintain nominally constant output-signal amplitude when recording speech signals. This circuitry automatically adjusts the MIC PGA gain as the input signal becomes overly loud or very weak, such as when a person speaking into a microphone moves closer to or farther from the microphone. The AGC algorithm has several programmable settings, including target gain, attack and decay time constants, noise threshold, and maximum PGA applicable, that allow the algorithm to be fine-tuned for any particular application. The algorithm uses the absolute average of the signal (which is the average of the absolute value of the signal) as a measure of the nominal amplitude of the output signal. Because the gain can be changed at the sample interval time, the AGC algorithm operates at the ADC_f_S clock rate.

Target level represents the nominal output level at which the AGC attempts to hold the ADC output signal. The TLV320AIC3110 allows programming of eight different target levels, which can be programmed from –5.5 dB to –24 dB relative to a full-scale signal. Because the TLV320AIC3110 reacts to the signal absolute average and not to peak levels, TI recommends that the target level be set with enough margin to avoid clipping at the occurrence of loud sounds.

An AGC low-pass filter is used to help determine the average level of the input signal. This average level is compared to the programmed detection levels in the AGC to provide the correct functionality. This low-pass filter is in the form of a first-order IIR filter. Programming this filter is done by writing to page 4 / register 2 through page 4 / register 7. Two 8-bit registers are used to form the 16-bit digital coefficient as shown on the register map. In this way, a total of six registers are programmed to form the three IIR coefficients.

Attack time determines how quickly the AGC circuitry reduces the PGA gain when the input signal is too loud. Programming the attack time is done by writing to page 0 / register 89, bits D7–D0.

Decay time determines how quickly the PGA gain is increased when the input signal is too low. Programming the decay time is done by writing to page 0 / register 90, bits D7–D0.

Noise threshold is a reference level. If the input speech average value falls below the noise threshold, the AGC considers it as a silence and hence brings down the gain to 0 dB in steps of 0.5 dB every sample period and sets the noise-threshold flag. The gain stays at 0 dB unless the input speech signal average rises above the noise-threshold setting. This ensures that noise is not amplified in the absence of speech. The noise-threshold level in the AGC algorithm is programmable from –30 dB to –90 dB for the microphone input. When the AGC noise threshold is set to –70 dB, –80 db, or –90 dB, the microphone input maximum PGA applicable setting must be greater than or equal to 11.5 dB, 21.5 dB, or 31.5 dB, respectively. This operation includes debounce and hysteresis to prevent the AGC gain from cycling between high gain and 0 dB when signals are near the noise threshold level. When the noise-threshold flag is set, the status of the gain applied by the AGC and the saturation flag has no meaning. Programming the noise debounce is done by writing to page 0 / register 91, bits D4–D0. Programming the signal debounce is done by writing to page 0 / register 92, bits D3–D0.

Max PGA applicable allows the user to restrict the maximum gain applied by the AGC. This can be used for limiting PGA gain in situations where environmental noise is greater than the programmed noise threshold. Microphone input maximum PGA can be programmed from 0 dB to 59.5 dB in steps of 0.5 dB. Programming the maximum PGA gain allowed by the AGC is done by writing to page 0 / register 88, bits D6–D0.

See Table 7-16 for various AGC programming options. AGC can be used only if the microphone input is routed to the ADC channel.

Figure 7-1 AGC Characteristics

The AGC settings should be set based on user and system conditions such as microphone selection and sensitivity, acoustics (plastics) around the microphone which affect the microphone pattern, expected distance and direction between microphone and sound source, and acoustic background noise.

One example of AGC code follows, but actual use of code should be verified based on application usage. Note that the AGC code should be set up before powering up the ADC.

7.3.9.3 Delta-Sigma ADC

The analog-to-digital converter has a delta-sigma modulator with an oversampling ratio (AOSR) up to 128. The ADC can support a maximum output rate of 192 kHz.

ADC power up is controlled by writing to page 0 / register 81, bit D7. An ADC power-up condition can be verified by reading page 0 / register 36, bit D6.

7.3.9.4 ADC Decimation Filtering and Signal Processing

The TLV320AIC3110 ADC channel includes built-in digital decimation filters to process the oversampled data from the delta-sigma modulator to generate digital data at the Nyquist sampling rate with high dynamic range. The decimation filter can be chosen from three different types, depending on the required frequency response, group delay, and sampling rate.

7.3.9.4.2 ADC Processing Blocks – Signal Chain Details

7.3.9.4.2.1 First-Order IIR, AGC, Filter A

Figure 7-2 Signal Chain for PRB_R4

7.3.9.4.2.2 Five Biquads, First-Order IIR, AGC, Filter A

Figure 7-3 Signal Chain for PRB_R5

7.3.9.4.2.3 25-Tap FIR, First-Order IIR, AGC, Filter A

Figure 7-4 Signal Chain for PRB_R6

7.3.9.4.2.4 First-Order IIR, AGC, Filter B

Figure 7-5 Signal Chain for PRB_R10

7.3.9.4.2.5 Three Biquads, First-Order IIR, AGC, Filter B

Figure 7-6 Signal Chain for PRB_R11

7.3.9.4.2.6 20-Tap FIR, First-Order IIR, AGC, Filter B

Figure 7-7 Signal Chain for PRB_R12

7.3.9.4.2.7 First-Order IIR, AGC, Filter C

Figure 7-8 Signal Chain for PRB_R16

7.3.9.4.2.8 Five Biquads, First-Order IIR, AGC, Filter C

Figure 7-9 Signal Chain for PRB_R17

7.3.9.4.2.9 25-Tap FIR, First-Order IIR, AGC, Filter C

Figure 7-10 Signal Chain for PRB_R18

7.3.9.4.3 User-Programmable Filters

Depending on the selected processing block, different types and orders of digital filtering are available. A first-order IIR filter is always available, and is useful to filter out possible dc components of the signal efficiently. Up to five biquad sections or, alternatively, FIR filters of up to 25 taps are available for specific processing blocks. The coefficients of the available filters are arranged as sequentially indexed coefficients.

The coefficients of these filters are each 16 bits wide, in 2s-complement format, and occupy two consecutive 8-bit registers in the register space. Specifically, the filter coefficients are in 1.15 (one dot 15) format with a range from –1.0 (0x8000) to 0.999969482421875 (0x7FFF), as shown in Figure 7-11.

Figure 7-11 1.15 2s-Complement Coefficient Format

7.3.9.4.3.1 First-Order IIR Section

The transfer function for the first-order IIR filter is given by Equation 1.

Equation 1.

The frequency response for the first-order IIR section with default coefficients is flat at a gain of 0 dB.

Table 7-18 ADC First-Order IIR Filter Coefficients

FILTER	FILTER COEFFICIENT	ADC COEFFICIENT	DEFAULT (RESET) VALUES
First-order IIR	N0	Page 4 / register 8 and page 4 / register 9	0x7FFF (decimal 1.0 – LSB value)
	N1	Page 4 / register 10 and page 4 / register 11	0x0000
	D1	Page 4 / register 12 and page 4 / register 13	0x0000

7.3.9.4.3.2 Biquad Section

The transfer function of each of the biquad filters is given by Equation 2.

Equation 2.

The default values for each biquad section yield an all-pass (flat) frequency response at a gain of 0 dB.

Table 7-19 ADC Biquad Filter Coefficients

FILTER	FILTER COEFFICIENT	FILTER COEFFICIENT RAM LOCATION	DEFAULT (RESET) VALUES
Biquad A	N0	Page 4 / register 14 and page 4 / register 15	0x7FFF (decimal 1.0 – LSB value)
	N1	Page 4 / register 16 and page 4 / register 17	0x0000
	N2	Page 4 / register 18 and page 4 / register 19	0x0000
	D1	Page 4 / register 20 and page 4 / register 21	0x0000
	D2	Page 4 / register 22 and page 4 / register 23	0x0000
Biquad B	N0	Page 4 / register 24 and page 4 / register 25	0x7FFF (decimal 1.0 – LSB value)
	N1	Page 4 / register 26 and page 4 / register 27	0x0000
	N2	Page 4 / register 28 and page 4 / register 29	0x0000
	D1	Page 4 / register 30 and page 4 / register 31	0x0000
	D2	Page 4 / register 32 and page 4 / register 33	0x0000
Biquad C	N0	Page 4 / register 34 and page 4 / register 35	0x7FFF (decimal 1.0 – LSB value)
	N1	Page 4 / register 36 and page 4 / register 37	0x0000
	N2	Page 4 / register 38 and page 4 / register 39	0x0000
	D1	Page 4 / register 40 and page 4 / register 41	0x0000
	D2	Page 4 / register 42 and page 4 / register 43	0x0000
Biquad D	N0	Page 4 / register 44 and page 4 / register 45	0x7FFF (decimal 1.0 – LSB value)
	N1	Page 4 / register 46 and page 4 / register 47	0x0000
	N2	Page 4 / register 48 and page 4 / register 49	0x0000
	D1	Page 4 / register 50 and page 4 / register 51	0x0000
	D2	Page 4 / register 52 and page 4 / register 53	0x0000
Biquad E	N0	Page 4 / register 54 and page 4 / register 55	0x7FFF (decimal 1.0 – LSB value)
	N1	Page 4 / register 56 and page 4 / register 57	0x0000
	N2	Page 4 / register 58 and page 4 / register 59	0x0000
	D1	Page 4 / register 60 and page 4 / register 61	0x0000
	D2	Page 4 / register 62 and page 4 / register 63	0x0000

7.3.9.4.3.3 FIR Section

Three of the available ADC processing blocks offer FIR filters for signal processing. Processing block PRB_R12 features a 20-tap FIR filter, whereas the processing blocks PRB_R6 and PRB_R18 each feature a 25-tap FIR filter.

Equation 3.

The coefficients of the FIR filters are 16-bit 2s-complement format (2 bytes each) and correspond to the ADC coefficient space as listed in Table 7-20. Note that the default (reset) coefficients are not valid for the FIR filter. When the FIR filter is used, all applicable coefficients must be reprogrammed by the user. To reprogram the FIR filter coefficients as an all-pass filter, write value 0x00 to page 4 / registers 24, 25, 34, 35, 44, 45, 54, and 55.

Table 7-20 ADC FIR Filter Coefficients

FILTER COEFFICIENT	FILTER COEFFICIENT RAM LOCATION	DEFAULT (RESET) VALUES – NOT VALID FOR THE FIR FILTER – MUST BE REPROGRAMMED BY USER
FIR0	Page 4 / register 14 and page 4 / register 15	0x7FFF (decimal 1.0 – LSB value)
FIR1	Page 4 / register 16 and page 4 / register 17	0x0000
FIR2	Page 4 / register 18 and page 4 / register 19	0x0000
FIR3	Page 4 / register 20 and page 4 / register 21	0x0000
FIR4	Page 4 / register 22 and page 4 / register 23	0x0000
FIR5	Page 4 / register 24 and page 4 / register 25	0x7FFF (decimal 1.0 – LSB value)
FIR6	Page 4 / register 26 and page 4 / register 27	0x0000
FIR7	Page 4 / register 28 and page 4 / register 29	0x0000
FIR8	Page 4 / register 30 and page 4 / register 31	0x0000
FIR9	Page 4 / register 32 and page 4 / register 33	0x0000
FIR10	Page 4 / register 34 and page 4 / register 35	0x7FFF (decimal 1.0 – LSB value)
FIR11	Page 4 / register 36 and page 4 / register 37	0x0000
FIR12	Page 4 / register 38 and page 4 / register 39	0x0000
FIR13	Page 4 / register 40 and page 4 / register 41	0x0000
FIR14	Page 4 / register 42 and page 4 / register 43	0x0000
FIR15	Page 4 / register 44 and page 4 / register 45	0x7FFF (decimal 1.0 – LSB value)
FIR16	Page 4 / register 46 and page 4 / register 47	0x0000
FIR17	Page 4 / register 48 and page 4 / register 49	0x0000
FIR18	Page 4 / register 50 and page 4 / register 51	0x0000
FIR19	Page 4 / registe 52 and page 4 / register 53	0x0000
FIR20	Page 4 / register 54 and page 4 / register 55	0x7FFF (decimal 1.0 – LSB value)
FIR21	Page 4 / register 56 and page 4 / register 57	0x0000
FIR22	Page 4 / register 58 and page 4 / register 59	0x0000
FIR23	Page 4 / register 60 and page 4 / register 61	0x0000
FIR24	Page 4 / register 62 and page 4 / register 63	0x0000

7.3.9.4.4 ADC Digital Decimation Filter Characteristics

The TLV320AIC3110 offers three different types of decimation filters. The integrated digital decimation filter removes high-frequency content and downsamples the audio data from an initial sampling rate of AOSR × f_S to the final output sampling rate of f_S. The decimation filtering is achieved using a higher-order CIC filter followed by linear-phase FIR filters. The decimation filter cannot be chosen by itself; it is implicitly set through the chosen processing block.

The following subsections describe the properties of the available filters A, B, and C.

7.3.9.4.4.1 Decimation Filter A

This filter is intended for use at sampling rates up to 48 kHz. When configuring this filter, the oversampling ratio of the ADC can either be 128 or 64. For highest performance, the oversampling ratio must be set to 128.

Filter A can also be used for 96 kHz at an AOSR of 64.

Table 7-21 ADC Decimation-Filter-A Specifications

PARAMETER	CONDITION	VALUE (TYPICAL)	UNIT
AOSR = 128
Filter gain pass band	0…0.39 fS	0.062	dB
Filter gain stop band	0.55…64 fS	–73	dB
Filter group delay		17/fS	s
Pass-band ripple, 8 ksps	0…0.39 fS	0.062	dB
Pass-band ripple, 44.1 ksps	0…0.39 fS	0.05	dB
Pass-band ripple, 48 ksps	0…0.39 fS	0.05	dB
AOSR = 64
Filter gain pass band	0…0.39 fS	0.062	dB
Filter gain stop band	0.55…32 fS	–73	dB
Filter group delay		17/fS	s
Pass-band ripple, 8 ksps	0…0.39 fS	0.062	dB
Pass-band ripple, 44.1 ksps	0…0.39 fS	0.05	dB
Pass-band ripple, 48 ksps	0…0.39 fS	0.05	dB
Pass-band ripple, 96 ksps	0…20 kHz	0.1	dB

Figure 7-12 ADC Decimation-Filter-A Frequency Response

7.3.9.4.4.2 Decimation Filter B

Filter B is intended to support sampling rates up to 96 kHz at an oversampling ratio of 64.

Table 7-22 ADC Decimation-Filter-B Specifications

PARAMETER	CONDITION	VALUE (TYPICAL)	UNIT
AOSR = 64
Filter gain pass band	0…0.39 fS	±0.077	dB
Filter gain stop band	0.60 fS…32 fS	–46	dB
Filter group delay		11/fS	s
Pass-band ripple, 8 ksps	0…0.39 fS	0.076	dB
Pass-band ripple, 44.1 ksps	0…0.39 fS	0.06	dB
Pass-band ripple, 48 ksps	0…0.39 fS	0.06	dB
Pass-band ripple, 96 ksps	0…20 kHz	0.11	dB

Figure 7-13 ADC Decimation-Filter-B Frequency Response

7.3.9.4.4.3 Decimation Filter C

Filter C along with an AOSR of 32 is specially designed for 192-ksps operation for the ADC. The pass band, which extends up to 0.11 × f_S (corresponding to 21 kHz), is suited for audio applications.

Table 7-23 ADC Decimation-Filter-C Specifications

PARAMETER	CONDITION	VALUE (TYPICAL)	UNIT
Filter gain from 0 to 0.11 fS	0…0.11 fS	±0.033	dB
Filter gain from 0.28 fS to 16 fS	0.28 fS…16 fS	–60	dB
Filter group delay		11/fS	s
Pass-band ripple, 8 ksps	0…0.11 fS	0.033	dB
Pass-band ripple, 44.1 ksps	0…0.11 fS	0.033	dB
Pass-band ripple, 48 ksps	0…0.11 fS	0.032	dB
Pass-band ripple, 96 ksps	0…0.11 fS	0.032	dB
Pass-band ripple, 192 ksps	0…20 kHz	0.086	dB

Figure 7-14 ADC Decimation-Filter-C Frequency Response

7.3.9.5 Updating ADC Digital Filter Coefficients During Record

When it is required to update the ADC digital filter coefficients during record, care must be taken to avoid click and pop noise or even a possible oscillation noise. These artifacts can occur if the ADC coefficients are updated without following the proper update sequence. The correct sequence is shown in Figure 7-15. The values for the times listed are conservative and should be used for software purposes.

Figure 7-15 Updating ADC Digital Filter Coefficients During Record

7.3.9.6 Digital Microphone Function

In addition to supporting analog microphones, the TLV320AIC3110 can also interface to one digital microphone using the mono ADC channel. Figure 7-16 shows the digital microphone interface block diagram and Figure 7-17 shows the timing diagram for the digital microphone interface.

Figure 7-16 Digital Microphone in the TLV320AIC3110

The TLV320AIC3110 outputs internal clock ADC_MOD_CLK on the GPIO1 pin (page 0 / register 51, bits D5–D2 = 1010). This clock can be connected to the external digital microphone device. The single-bit output of the external digital microphone device can be connected to the DIN pin. Internally, the TLV320AIC3110 latches the steady value of the mono ADC data on the rising edge of ADC_MOD_CLK.

Figure 7-17 Timing Diagram for Digital Microphone Interface

When the digital microphone mode is enabled, the analog section of the ADC can be powered down and bypassed for power efficiency. The AOSR value for the ADC channel must be configured to select the desired decimation ratio to be achieved, based on the external digital microphone properties.

7.3.9.7 DC Measurement

The TLV320AIC3110 supports a highly flexible dc-measurement feature using the high-resolution oversampling and noise-shaping ADC. This mode can be used when the ADC channel is not used for the voice/audio record function. This mode can be enabled by programming page 0 / register 102, bit D7. The converted data is 24 bits, using the 2.22 numbering format. The value of the converted data for the ADC channel can be read back from page 0 / register 104 through page 1 / register 106. Before reading back the converted data, page 0 / register 103, bit D6 must be programmed to 1 in order to latch the converted data into the read-back registers. After the converted data is read back, page 0 / register 103, bit D6 must be immediately reset to 0. In dc-measurement mode, two measurement modes are supported.

Mode A

In dc-measurement mode A, a variable-length averaging filter is used. The length of averaging filter D can be programmed from 1 to 20 by programming page 0 / register 102, bits D4–D0. To choose mode A, page 0 / register 102, bit D5 must be programmed to 0.

Mode B

To choose mode B, page 0 / register 102, bit D5 must be programmed to 1. In dc-measurement mode B, a first-order IIR filter is used. The coefficients of this filter are determined by D, page 0 / register 102, bits D4–D0. The nature of the filter is given in Table 7-24.

By programming page 0 / register 103, bit D5 to 1, the averaging filter is periodically reset after 2^R number of ADC_MOD_CLK periods, where R is programmed in page 0 / register 103, bits D4–D0. When page 0 / register 103, bit D5 is set to 1, then the value of D should be less than the value of R. When page 0 / register 103, bit D5 is programmed to 0, the averaging filter is never reset.

7.3.10.1 DAC

The TLV320AIC3110 stereo-audio DAC supports data rates from 8 kHz to 192 kHz. Each channel of the stereo audio-DAC consists of a signal-processing engine with fixed processing blocks, a digital interpolation filter, a multibit digital delta-sigma modulator, and an analog reconstruction filter. The DAC is designed to provide enhanced performance at low sampling rates through increased oversampling and image filtering, thereby keeping quantization noise generated within the delta-sigma modulator and signal images strongly suppressed within the audio band to beyond 20 kHz. To handle multiple input rates and optimize power dissipation and performance, the TLV320AIC3110 device allows the system designer to program the oversampling rates over a wide range from 1 to 1024 by configuring page 0 / register 13 and page 0 / register 14. The system designer can choose higher oversampling ratios for lower input data rates and lower oversampling ratios for higher input data rates.

The TLV320AIC3110 DAC channel includes a built-in digital interpolation filter to generate oversampled data for the delta-sigma modulator. The interpolation filter can be chosen from three different types, depending on required frequency response, group delay, and sampling rate.

DAC power up is controlled by writing to page 0 / register 63, bit D7 for the left channel and bit D6 for the right channel. The left-channel DAC clipping flag is provided as a read-only bit on page 0 / register 39, bit D7. The right-channel DAC clipping flag is provided as a read-only bit on page 0 / register 39, bit D6.

7.3.10.1.2 DAC Processing Blocks — Details

7.3.10.1.2.1 Three Biquads, Filter A

Figure 7-18 Signal Chain for PRB_P1 and PRB_P4

7.3.10.1.2.2 Six Biquads, First-Order IIR, DRC, Filter A or B

Figure 7-19 Signal Chain for PRB_P2, PRB_P5, PRB_P10, and PRB_P15

7.3.10.1.2.3 Six Biquads, First-Order IIR, Filter A or B

Figure 7-20 Signal Chain for PRB_P3, PRB_P6, PRB_P11, and PRB_P16

7.3.10.1.2.4 IIR, Filter B or C

Figure 7-21 Signal Chain for PRB_P7, PRB_P12, PRB_P17, and PRB_P20

7.3.10.1.2.5 Four Biquads, DRC, Filter B

Figure 7-22 Signal Chain for PRB_P8 and PRB_P13

7.3.10.1.2.6 Four Biquads, Filter B

Figure 7-23 Signal Chain for PRB_P9 and PRB_P14

7.3.10.1.2.7 Four Biquads, First-Order IIR, DRC, Filter C

Figure 7-24 Signal Chain for PRB_P18 and PRB_P21

7.3.10.1.2.8 Four Biquads, First-Order IIR, Filter C

Figure 7-25 Signal Chain for PRB_P19 and PRB_P22

7.3.10.1.2.9 Two Biquads, 3D, Filter A

NOTE:

A_L means biquad A of the left channel, and similarly, B_R means biquad B of the right channel.

Figure 7-26 Signal Chain for PRB_P23

7.3.10.1.2.10 Five Biquads, DRC, 3D, Filter A

Figure 7-27 Signal Chain for PRB_P24

7.3.10.1.2.11 Five Biquads, DRC, 3D, Beep Generator, Filter A

Figure 7-28 Signal Chain for PRB_P25

7.3.10.1.3 DAC User-Programmable Filters

Based on the selected processing block, different types and orders of digital filtering are available. Up to six biquad sections are available for specific processing blocks.

The coefficients of the available filters are arranged as sequentially-indexed coefficients in two banks. If adaptive filtering is chosen, the coefficient banks can be switched in real time.

When the DAC is running, the user-programmable filter coefficients are locked and cannot be accessed for either read or write.

However, the TLV320AIC3110 device offers an adaptive filter mode as well. Setting page 8 / register 1, bit D2 = 1 turns on double buffering of the coefficients. In this mode, filter coefficients are updated through the host and activated without stopping and restarting the DAC which enables advanced adaptive filtering applications.

In the double-buffering scheme, all coefficients are stored in two buffers (buffers A and B). When the DAC is running and the adaptive filtering mode is turned on, setting page 8 / register 1, bit D0 = 1 switches the coefficient buffers at the next start of a sampling period. This bit is set back to 0 after the switch occurs. At the same time, page 8 / register 1, bit D1 toggles.

The flag in page 8 / register 1, bit D1 indicates which of the two buffers is actually in use.

Page 8 / register 1, bit D1 = 0: buffer A is in use by the DAC engine; bit D1 = 1: buffer B is in use.

While the device is running, coefficient updates are always made to the buffer not in use by the DAC, regardless of the buffer to which the coefficients have been written.

Table 7-26 Adaptive-Mode Filter-Coefficient Buffer Switching

DAC POWERED UP	PAGE 8 / REGISTER 1, BIT D1	COEFFICIENT BUFFER IN USE	WRITING TO	UPDATES
No	0	None	Page 8, Reg 2–3, buffer A	Page 8, Reg 2–3, buffer A
No	0	None	Page 12, Reg 2–3, buffer B	Page 12, Reg 2–3, buffer B
Yes	0	Buffer A	Page 8, Reg 2–3, buffer A	Page 12, Reg 2–3, buffer B
Yes	0	Buffer A	Page 12, Reg 2–3, buffer B	Page 12, Reg 2–3, buffer B
Yes	1	Buffer B	Page 8, Reg 2–3, buffer A	Page 8, Reg 2–3, buffer A
Yes	1	Buffer B	Page 12, Reg 2–3, buffer B	Page 8, Reg 2–3, buffer A

The user-programmable coefficients for the DAC Processing Blocks are defined on page 8 and page 9 for buffer A and page 12 and page 13 for buffer B.

The coefficients of these filters are each 16-bit, 2s-complement format, occupying two consecutive 8-bit registers in the register space. Specifically, the filter coefficients are in 1.15 (one dot 15) format with a range from –1.0 (0x8000) to 0.999969482421875 (0x7FFF) as shown in Figure 7-11.

7.3.10.1.3.1 First-Order IIR Section

The IIR is of first order and its transfer function is given by Equation 4.

Equation 4.

The frequency response for the first-order IIR section with default coefficients is flat.

Table 7-27 DAC IIR Filter Coefficients

FILTER	COEFFICIENT	LEFT DAC CHANNEL	RIGHT DAC CHANNEL	DEFAULT (RESET) VALUE
First-order IIR	N0	Page 9 / register 2 and page 9 / register 3	Page 9 / register 8 and page 9 / register 9	0x7FFF (decimal 1.0 – LSB value)
	N1	Page 9 / register 4 and page 9 / register 5	Page 9 / register 10 and page 9 / register 11	0x0000
	D1	Page 9 / register 6 and page 9 / register 7	Page 9 / register 12 and page 9 / register 13	0x0000

7.3.10.1.3.2 Biquad Section

The transfer function of each of the biquad filters is given by Equation 5.

Equation 5.

Table 7-28 DAC Biquad Filter Coefficients

FILTER	COEFFICIENT	LEFT DAC CHANNEL	RIGHT DAC CHANNEL	DEFAULT (RESET) VALUE
Biquad A	N0	Page 8 / register 2 and page 8 / register 3	Page 8 / register 66 and page 8 / register 67	0x7FFF (decimal 1.0 – LSB value)
	N1	Page 8 / register 4 and page 8 / register 5	Page 8 / register 68 and page 8 / register 69	0x0000
	N2	Page 8 / register 6 and page 8 / register 7	Page 8 / register 70 and page 8 / register 71	0x0000
	D1	Page 8 / register 8 and page 8 / register 9	Page 8 / register 72 and page 8 / register 73	0x0000
	D2	Page 8 / register 10 and page 8 / register 11	Page 8 / register 74 and page 8 / register 75	0x0000
Biquad B	N0	Page 8 / register 12 and page 8 / register 13	Page 8 / register 76 and page 8 / register 77	0x7FFF (decimal 1.0 – LSB value)
	N1	Page 8 / register 14 and page 8 / register 15	Page 8 / register 78 and page 8 / register 79	0x0000
	N2	Page 8 / register 16 and page 8 / register 17	Page 8 / register 80 and page 8 / register 81	0x0000
	D1	Page 8 / register 18 and page 8 / register 19	Page 8 / register 82 and page 8 / register 83	0x0000
	D2	Page 8 / register 20 and page 8 / register 21	Page 8 / register 84 and page 8 / register 85	0x0000
Biquad C	N0	Page 8 / register 22 and page 8 / register 23	Page 8 / register 86 and page 8 / register 87	0x7FFF (decimal 1.0 – LSB value)
	N1	Page 8 / register 24 and page 8 / register 25	Page 8 / register 88 and page 8 / register 89	0x0000
	N2	Page 8 / register 26 and page 8 / register 27	Page 8 / register 90 and page 8 / register 91	0x0000
	D1	Page 8 / register 28 and page 8 / register 29	Page 8 / register 92 and page 8 / register 93	0x0000
	D2	Page 8 / register 30 and page 8 / register 31	Page 8 / register 94 and page 8 / register 95	0x0000
Biquad D	N0	Page 8 / register 32 and page 8 / register 33	Page 8 / register 96 and page 8 / register 97	0x7FFF (decimal 1.0 – LSB value)
	N1	Page 8 / register 34 and page 8 / register 35	Page 8 / register 98 and page 8 / register 99	0x0000
	N2	Page 8 / register 36 and page 8 / register 37	Page 8 / register 100 and page 8 / register 101	0x0000
	D1	Page 8 / register 38 and page 8 / register 39	Page 8 / register 102 and page 8 / register 103	0x0000
	D2	Page 8 / register 40 and page 8 / register 41	Page 8 / register 104 and page 8 / register 105	0x0000
Biquad E	N0	Page 8 / register 42 and page 8 / register 43	Page 8 / register 106 and page 8 / register 107	0x7FFF (decimal 1.0 – LSB value)
	N1	Page 8 / register 44 and page 8 / register 45	Page 8 / register 108 and page 8 / register 109	0x0000
	N2	Page 8 / register 46 and page 8 / register 47	Page 8 / register 110 and page 8 / register 111	0x0000
	D1	Page 8 / register 48 and page 8 / register 49	Page 8 / register 112 and page 8 / register 113	0x0000
	D2	Page 8 / register 50 and page 8 / register 51	Page 8 / register 114 and page 8 / register 115	0x0000
Biquad F	N0	Page 8 / register 52 and page 8 / register 53	Page 8 / register 116 and page 8 / register 117	0x7FFF (decimal 1.0 – LSB value)
	N1	Page 8 / register 54 and page 8 / register 55	Page 8 / register 118 and page 8 / register 119	0x0000
	N2	Page 8 / register 56 and page 8 / register 57	Page 8 / register 120 and page 8 / register 121	0x0000
	D1	Page 8 / register 58 and page 8 / register 59	Page 8 / register 122 and page 8 / register 123	0x0000
	D2	Page 8 / register 60 and page 8 / register 61	Page 8 / register 124 and page 8 / register 125	0x0000

7.3.10.1.4 DAC Interpolation Filter Characteristics

7.3.10.1.4.1 Interpolation Filter A

Filter A is designed for an f_S up to 48 ksps with a flat passband of 0 to 20 kHz.

Table 7-29 Specification for DAC Interpolation Filter A

PARAMETER	CONDITION	VALUE (TYPICAL)	UNIT
Filter-gain pass band	0 … 0.45 fS	±0.015	dB
Filter-gain stop band	0.55… 7.455 fS	–65	dB
Filter group delay		21 / fS	s

Figure 7-29 Frequency Response of DAC Interpolation Filter A

7.3.10.1.4.2 Interpolation Filter B

Filter B is specifically designed for an f_S of up to 96 ksps. Thus, the flat passband region easily covers the required audio band of 0 to 20 kHz.

Table 7-30 Specification for DAC Interpolation Filter B

PARAMETER	CONDITION	VALUE (TYPICAL)	UNIT
Filter-gain pass band	0 … 0.45 fS	±0.015	dB
Filter-gain stop band	0.55… 3.45 fS	–58	dB
Filter group delay		18 / fS	s

Figure 7-30 Frequency Response of Channel Interpolation Filter B

7.3.10.1.4.3 Interpolation Filter C

Filter C is specifically designed for the 192-ksps mode. The pass band extends up to 0.4 × f_S (corresponds to 80 kHz), more than sufficient for audio applications.

Table 7-31 Specification for DAC Interpolation Filter C

PARAMETER	CONDITION	VALUE (TYPICAL)	UNIT
Filter-gain pass band	0 … 0.35 fS	±0.03	dB
Filter-gain stop band	0.6… 1.4 fS	–43	dB
Filter group delay		13 / fS	s

Figure 7-31 Frequency Response of DAC Interpolation Filter C

7.3.10.2 DAC Digital-Volume Control

The DAC has a digital-volume control block which implements programmable gain. Each channel has an independent volume control that can be varied from 24 dB to –63.5 dB in 0.5-dB steps. The left-channel DAC volume is controlled by writing to page 0 / register 65, bits D7–D0. The right-channel DAC volume can be controlled by writing to page 0 / register 66, bits D7–D0. DAC muting and setting up a master gain control to control both channels occurs by writing to page 0 / register 64, bits D3–D0. The gain is implemented with a soft-stepping algorithm, which only changes the actual volume by 0.125 dB per input sample, either up or down, until the desired volume is reached. The rate of soft-stepping is slowed to one step per two input samples by writing to page 0 / register 63, bits D1–D0. Note that the default source for volume-control level settings is control by register writes (page 0 / register 65 and page 0 / register 66 to control volume). Use of the VOL/MICDET pin to control the DAC volume is ignored until the volume control source selected has been changed to pin control (page 0 / register 116, bit D7 = 1). This functionality is shown in .

During soft-stepping, the host does not receive a signal when the DAC has been completely muted. This may be important if the host must mute the DAC before making a significant change, such as changing sample rates. In order to help with this situation, the device provides a flag back to the host through a read-only register, page 0 / register 38, bit D4 for the left channel and bit D0 for the right channel. This information alerts the host when the part has completed the soft-stepping and the actual volume has reached the desired volume level. The soft-stepping feature can be disabled by writing to page 0 / register 63, bits D1–D0.

If soft-stepping is enabled, the CODEC_CLKIN signal must be kept active until the DAC power-up flag is cleared. When this flag is cleared, the internal DAC soft-stepping process is complete, and CODEC_CLKIN can be stopped if desired. (The analog volume control can be ramped down using an internal oscillator.)

7.3.10.3 Volume Control Pin

The range of voltages used by the 7-bit SAR ADC is shown in Section 5.5.

The volume-control pin is not enabled by default but is enabled by writing 1 to page 0 / register 116, bit D7. The default DAC volume control uses software control of the volume, which occurs if page 0 / register 116, bit D7 = 0. Soft-stepping the volume level is set up by writing to page 0 / register 63, bits D1–D0.

When the volume-pin function is used, a 7-bit Vol ADC reads the voltage on the VOL/MICDET pin and updates the digital volume control by overwriting the current value of the volume control. The new volume setting which has been applied because of a change of voltage on the volume control pin is read on page 0 / register 117, bits D6–D0. The 7-bit Vol ADC clock source is selected on page 0 / register 116, bit D6. The update rate is programmed on page 0 / register 116, bits D2–D0 for this 7-bit SAR ADC.

Table 7-32 lists The VOL/MICDET pin gain mapping.

Figure 7-32 shows the VOL/MICDET pin connection and functionality.

Figure 7-32 Digital Volume Controls for Beep Generator and DAC Play Data

As shown in Table 7-32, the VOL/MICDET pin has a range of volume control from 18 dB down to –63 dB, and mute. However, if less maximum gain is required, then a smaller range of voltage must be applied to the VOL/MICDET pin. Applying a smaller range of voltage occurs by increasing the value of R2 relative to the value of (P1 + R1), so that more voltage is available at the bottom of P1. The circuit must also be designed such that for the values of R1, R2, and P1 chosen, the maximum voltage (top of the potentiometer) does not exceed AVDD/2 (see Figure 7-32). The recommended values for R1, R2, and P1 for several maximum gains are shown in Table 7-33.

7.3.10.4 Dynamic Range Compression

Typical music signals are characterized by crest factors, the ratio of peak signal power to average signal power, of 12 dB or more. To avoid audible distortions due to clipping of peak signals, the gain of the DAC channel must be adjusted so as not to cause hard clipping of peak signals. As a result, during nominal periods, the applied gain is low, causing the perception that the signal is not loud enough. To overcome this problem, dynamic range conpression (DRC) in the TLV320AIC3110 continuously monitors the output of the DAC digital volume control to detect its power level relative to 0 dBFS. When the power level is low, DRC increases the input signal gain to make it sound louder. At the same time, if a peaking signal is detected, it autonomously reduces the applied gain to avoid hard clipping. This results in sounds more pleasing to the ear as well as sounding louder during nominal periods.

The DRC functionality in the TLV320AIC3110 is implemented by a combination of processing blocks in the DAC channel as described in Section 7.3.10.1.2.

DRC can be disabled by writing to page 0 / register 68, bits D6–D5.

DRC typically works on the filtered version of the input signal. The input signals have no audio information at dc and extremely low frequencies; however, they can significantly influence the energy estimation function in the dynamic range compressor (the DRC). Also, most of the information about signal energy is concentrated in the low-frequency region of the input signal.

To estimate the energy of the input signal, the signal is first fed to the DRC high-pass filter and then to the DRC low-pass filter. These filters are implemented as first-order IIR filters given by

Equation 6.

Equation 7.

The coefficients for these filters are 16 bits wide in 2s-complement format and are user-programmable through register write as given in Table 7-34.

The default values of these coefficients implement a high-pass filter with a cutoff at 0.00166 × DAC_f_S, and a low-pass filter with a cutoff at 0.00033 × DAC_f_S.

The output of the DRC high-pass filter is fed to the processing block selected for the DAC channel. The absolute value of the DRC LPF filter is used for energy estimation within the DRC.

The gain in the DAC digital volume control is controlled by page 0 / register 65 and page 0 / register 66. When the DRC is enabled, the applied gain is a function of the digital volume control register setting and the output of the DRC.

The DRC parameters are described in sections that follow.

7.3.10.5 Headset Detection

The TLV320AIC3110 device includes extensive capability to monitor a headphone, microphone, or headset jack, to determine if a plug has been inserted into the jack, and then determine what type of headset or headphone is wired to the plug. The device also includes the capability to detect a button press, even, for example, when starting calls on mobile phones with headsets. Figure 7-33 shows the circuit configuration to enable this feature.

Figure 7-33 Jack Connections for Headset Detection

Headset Detection is enabled by programming page 0 / register 67, bit D1. In order to avoid false detections because of mechanical vibrations in headset jacks or microphone buttons, a debounce function is provided for glitch rejection. For the case of headset insertion, a debounce function with a range of 32 ms to 512 ms is provided. This can be programmed through page 0 / register 67, bits D4–D2. For improved button-press detection, the debounce function has a range of 8 ms to 32 ms by programming page 0 / register 67, bits D1–D0.

The TLV320AIC3110 device also provides feedback to the user when a button press or a headset insertion or removal event is detected through the register-readable flags as well as an interrupt on the I/O pins. The value in page 0 / register 46, bits D5–D4 provides the instantaneous state of button press and headset insertion. Page 0 / register 44, bit D5 is a sticky (latched) flag that is set when the button-press event is detected. Page 0 / register 44, bit D4 is a sticky flag which is set when the headset insertion or removal event is detected. These sticky flags are set by the event occurrence, and are reset only when read. This requires polling page 0 / register 44. To avoid polling and the associated overhead, the TLV320AIC3110 device also provides an interrupt feature, whereby events can trigger the INT1, the INT2, or both interrupts. These interrupt events can be routed to one of the digital output pins. See Section 7.3.10.6 for details.

The TLV320AIC3110 device not only detects a headset insertion event, but also is able to distinguish between the different headsets inserted, such as stereo headphones or cellular headphones. After the headset-detection event, the user can read page 0 / register 67, bits D6–D5 to determine the type of headset inserted.

The headset detection block requires AVDD to be powered. The headset detection feature in the TLV320AIC3110 device is achieved with very low power overhead, requiring less than 20 μA of additional current from the AVDD supply.

7.3.10.6 Interrupts

Some specific events in the TLV320AIC3110 device that can require host processor intervention are used to trigger interrupts to the host processor. This avoids polling the status-flag registers continuously. The TLV320AIC3110 device has two defined interrupts, INT1 and INT2, that are configured by programming page 0 / register 48 and page 0 / register 49. A user can configure interrupts INT1 and INT2 to be triggered by one or many events, such as:

• Headset detection
• Button press
• DAC DRC signal exceeding threshold
• Noise detected by AGC
• Overcurrent condition in headphone drivers and speaker drivers
• Data overflow in the ADC and DAC processing blocks and filters
• DC measurement data available

Each of these INT1 and INT2 interrupts can be routed to output pins GPIO1 or DOUT. These interrupt signals can either be configured as a single pulse or a series of pulses by programming page 0 / register 48, bit D0 and page 0 / register 49, bit D0. If the user configures the interrupts as a series of pulses, the events trigger the start of pulses that stop when the flag registers in page 0 / registers 44, 45, and 50 are read by the user to determine the cause of the interrupt.

7.3.10.7 Key-Click Functionality With Digital Sine-Wave Generator (PRB_P25)

A special algorithm has been included in the digital signal processing block PRB_P25 for generating a digital sine-wave signal that is sent to the DAC. The digital sine-wave generator is also referred to as the beep generator in this document.

This functionality is intended for generating key-click sounds for user feedback. The sine-wave generator is very flexible (see Table 7-36) and is completely register programmable. Programming page 0 / register 71 through page 0 / register 79 (8 bits each) completely controls the functionality of this generator and allows for differentiating sounds.

The two registers used for programming the 16-bit sine-wave coefficient are page 0 / register 76 and page 0 / register 77. The two registers used for programming the 16-bit cosine-wave coefficient are page 0 / register 78 and page 0 / register 79. This coefficient resolution allows virtually any frequency of sine wave in the audio band to be generated, up to f_S / 2.

The three registers used to control the length of the sine-burst waveform are page 0 / register 73 through page 0 / register 75. The resolution (bit) in the registers of the sine-burst length is one sample time, so this allows great control on the overall time of the sine-burst waveform. This 24-bit length timer supports
16 777 215 sample times. For example, if f_S is set at 48 kHz, and the register value equals 96 000 d (01 7700h), then the sine burst lasts exactly 2 seconds. The default settings for the tone generator, based on using a sample rate of 48 kHz, are 1-kHz (approximately) sine wave, with a sine-burst length of five cycles (5 ms).

Two registers are used to control the left sine-wave volume and the right sine-wave volume independently. The 6-bit digital volume control used allows level control of 2 dB to –61 dB in 1-dB steps. The left-channel volume is controlled by writing to page 0 / register 71, bits D5–D0. The right-channel volume is controlled by writing to page 0, register 72, bits D5–D0. A master volume control that controls the left and right channels of the beep generator are set up by writing to page 0 / register 72, bits D7–D6. The default volume control setting is 2 dB, which provides the maximum tone-generator output level.

For generating other tones, the three tone-generator coefficients are found by running the following script using MATLAB™ :

where,

Fin = Beep frequency desired
Fs = Sample rate
Cycle = Number of beep (sine wave) cycles that are required
dec2hex = Decimal to hexadecimal conversion function

NOTES:

1. Fin must be less than Fs / 4.
2. For the sine and cosine values, if the number of bits is less than the full 16-bit value, then the unused MSBs must be written as 0s.
3. For the beep-length values, if number of bits is less than the full 24-bit value, then the unused MSBs must be written as 0s.

Following the beep-volume control is a digital mixer that mixes in a playback data stream whose level has already been set by the DAC volume control. Therefore, once the key-click volume level is set, the key-click volume is not affected by the DAC volume control, which is the main control available to the end user. shows this functionality.

Following the DAC, the signal can be further scaled by the analog output volume control and power-amplifier level control.

To insert a beep in the middle of an already-playing signal over DAC, use the following sequence.

Before the beep is desired, program the desired beep frequency, volume, and length in the configuration registers. When a beep is desired, use the example configuration script.

Note that in this scheme the audio signal on the DAC is temporarily muted to enable beep generation. Because powering down of NDAC clock divider is required, do not use the DAC_CLK or DAC_MOD_CLK for generation of I²S clocks.

7.3.10.8 Programming DAC Digital Filter Coefficients

The digital filter coefficients must be programmed through the I²C interface. All digital filtering for the DAC signal path must be loaded into the RAM before the DAC is powered on. Note that default ALLPASS filter coefficients for programmable biquads are located in boot ROM. The boot ROM automatically loads the default values into the RAM following a hardware reset (toggling the RESET pin) or after a software reset. After resetting the device, loading boot ROM coefficients into the digital filters requires 100 μs of programming time. During this time, reading or writing to page 8 through page 15 for updating DAC filter coefficient values is not permitted. The DAC should not be powered up until after all of the DAC configurations have been done by the system microprocessor.

7.3.10.9 Updating DAC Digital Filter Coefficients During PLAY

When it is required to update the DAC digital filter coefficients or beep generator during play, care must be taken to avoid click and pop noise or even a possible oscillation noise. These artifacts can occur if the DAC coefficients are updated without following the proper update sequence. The correct sequence is shown in Figure 7-34. The values for times listed in Figure 7-34 are conservative and should be used for software purposes.

There is also an adaptive mode, in which DAC coefficients can be updated while the DAC is on. For details, see Section 7.3.10.1.3.

Figure 7-34 Example Flow For Updating DAC Digital Filter Coefficients During Play

7.3.10.10 Digital Mixing and Routing

The TLV320AIC3110 has four digital mixing blocks. Each mixer can provide either mixing or multiplexing of the digital audio data. This arrangement of digital mixers allows independent volume control for both the playback data and the key-click sound. The first set of mixers can be used to make monaural signals from left and right audio data, or they can be used to swap channels to the DAC. This function is accomplished by selecting left audio data for the right DAC input, and right data for the left DAC input. The second set of mixers provides mixing of the audio data stream and the key-click sound. The digital routing can be configured by writing to page 0 / register 63, bits D5–D4 for the left channel and bits D3–D2 for the right channel.

Because the key-click function uses the digital signal processing block, the CODEC_CLKIN, DAC, analog volume control, and output driver must be powered on for the key-click sound to occur.

7.3.10.11 Analog Audio Routing

The TLV320AIC3110 has the capability to route the DAC output to either the headphone or the speaker output. If desirable, both output drivers can operate at the same time while playing at different volume levels. The TLV320AIC3110 provides various digital routing capabilities, allowing digital mixing or even channel swapping in the digital domain. All analog outputs other than the selected ones can be powered down for optimal power consumption.

7.3.10.12 Analog Outputs

Various analog routings are supported for playback. All the options can be conveniently viewed on the functional block diagram, .

7.3.10.13 Audio-Output Stage-Power Configurations

After the device has been configured (following a RESET) and the circuitry has been powered up, the audio output stage can be powered up and powered down by register control.

These functions soft-start automatically. By using these register controls, controlling all four output stages independently is possible.

See Table 7-39 for register control of audio output stage power configurations.

7.3.10.14 Example Register Setup to Play Digital Data Through DAC and Headphone/Speaker Outputs

A typical EVM I²C register control script follows to show how to set up the TLV320AIC3110 in playback mode with f_S = 44.1 kHz and MCLK = 11.2896 MHz.

Table 7-40 CODEC CLKIN Clock Dividers

Table 7-41 Maximum TLV320AIC3110 Clock Frequencies

7.3.11.1 PLL

For lower power consumption, the best process is to derive the internal audio processing clocks using the simple dividers. When the input MCLK or other source clock is not an integer multiple of the audio processing clocks then using the on-board PLL is necessary. The TLV320AIC3110 fractional PLL generates an internal master clock that produces the processing clocks required by the ADC, DAC, and digital processing blocks. The programmability of this PLL allows operation from a wide variety of clocks that may be available in the system.

The PLL input supports clocks varying from 512 kHz to 20 MHz and is register-programmable to enable generation of the required sampling rates with fine resolution. The PLL turns on by writing to page 0 / register 5, bit D7. When the PLL is enabled, the PLL output clock, PLL_CLK, is given by Equation 9.

Equation 9.

where

• R = 1, 2, 3, ..., 16 (page 0 / register 5, default value = 1)
• J = 1, 2,3, … , 63, (page 0 / register 6, default value = 4)
• D = 0, 1, 2, …, 9999 (page 0 / register 7 and page 0 / register 8, default value = 0)
• P = 1, 2, 3, …, 8 (page 0 / register 5, default value = 1)

The PLL turns on through page 0 / register 5, bit D7. The variable P is programmed through page 0 / register 5, bits D6–D4. The variable R is programmed through page 0 / register 5, bits D3–D0. The variable J is programmed through page 0 / register 6, bits D5–D0. The variable D is 14 bits and is programmed into two registers. The MSB portion is programmed through page 0 / register 7, bits D5–D0, and the LSB portion is programmed thrugh page 0 / register 8, bits D7–D0. For proper update of the D-divider value, page 0 / register 7 must be programmed first, followed immediately by page 0 / register 8. The new value of D does not take effect unless the write to page 0 / register 8 is complete.

When the PLL is enabled, the following conditions must be satisfied:

• When the PLL is enabled and D = 0, the following conditions must be satisfied for PLL_CLKIN:
Equation 10.

80 MHz ≤ (PLL_CLKIN × J.D. × R / P) ≤ 110 MHz




4 ≤ R × J ≤ 259

• When the PLL is enabled and D ≠ 0, the following conditions must be satisfied for PLL_CLKIN:
Equation 11.

80 MHz ≤ PLL_CLKIN × J.D. × R / P ≤ 110 MHz




R = 1

The PLL can power up independently from the ADC and DAC blocks, and can also be used as a general-purpose PLL by routing the PLL output to the GPIO output. After powering up the PLL, PLL_CLK is available typically after 10 ms.

The clocks for the codec and various signal processing blocks, CODEC_CLKIN, are generated from the MCLK input, BCLK input, GPIO input, or PLL_CLK (page 0 / register 4, bits D1–D0).

If CODEC_CLKIN is derived from the PLL, then the PLL must be powered up first and powered down last.

Table 7-42 lists several example cases of typical PLL_CLKIN rates and how to program the PLL to achieve a sample rate f_S of either 44.1 kHz or 48 kHz.

7.3.13.1 Digital Audio Interface

Audio data is transferred between the host processor and the TLV320AIC3110 device through the digital audio data, serial interface, or audio bus. The audio bus on this device is very flexible, including left- or right-justified data options, support for I²S or DSP protocols, programmable data length options, a TDM mode for multichannel operation, very flexible master and slave configurability for each bus-clock line, and the ability to communicate with multiple devices within a system directly.

The audio bus of the TLV320AIC3110 device can be configured for left-justified or right-justified, I²S, DSP, or TDM modes of operation, where communication with standard telephony interfaces is supported within the TDM mode. These modes are all MSB-first, with data width programmable as 16, 20, 24, or 32 bits by configuring page 0 / register 27, bits D5–D4. In addition, the word clock and bit clock can be independently configured in either master or slave mode, for flexible connectivity to a wide variety of processors. The word clock defines the beginning of a frame, and can be programmed as either a pulse or a square-wave signal. The frequency of this clock corresponds to the maximum of the selected ADC and DAC sampling frequencies.

The bit clock is used to clock-in and clock-out the digital audio data across the serial bus. When in master mode, this signal can be programmed to generate variable clock pulses by controlling the bit-clock divider in page 0 / register 30 (see Figure 7-35). The number of bit-clock pulses in a frame can require adjustment to accommodate various word lengths as well as to support the case when multiple TLV320AIC3110s share the same audio bus.

The TLV320AIC3110 device also includes a feature to offset the position of start-of-data transfer with respect to the word clock. This offset is controlled in terms of number of bit-clocks and can be programmed in page 0 / register 28.

The TLV320AIC3110 device also has the feature of inverting the polarity of the bit clock used for transferring the audio data as compared to the default clock polarity used. This feature can be used independently of the mode of audio interface chosen. This can be configured through page 0 / register 29, bit D3.

The TLV320AIC3110 device further includes programmability (page 0 / register 27, bit D0) to place the DOUT line in the high-impedance state during all bit clocks when valid data is not being sent. By combining this capability with the ability to program at what bit clock in a frame the audio data begins, time-division multiplexing (TDM) is accomplished, enabling the use of multiple codecs on a single audio serial data bus. When the audio serial data bus is powered down while configured in master mode, the pins associated with the interface are put into a high-impedance output condition.

By default, when the word clocks and bit clocks are generated by the TLV320AIC3110 device, these clocks are active only when the codecs (ADC, DAC or both) are powered up within the device. This is done to save power. However, it also supports a feature when both the word clocks and bit clocks can be active even when the codec in the device is powered down. This is useful when using the TDM mode with multiple codecs on the same bus, or when word clocks or bit clocks are used in the system as general-purpose clocks.

7.3.13.1.1 Right-Justified Mode

The audio interface of the TLV320AIC3110 can enter the right-justified mode by programming page 0 / register 27, bits D7–D6 = 10. In right-justified mode, the LSB of the left channel is valid on the rising edge of the bit clock preceding the falling edge of the word clock. Similarly, the LSB of the right channel is valid on the rising edge of the bit clock preceding the rising edge of the word clock.

Figure 7-39 Timing Diagram for Right-Justified Mode

For the right-justified mode, the number of bit clocks per frame should be greater-than or equal-to twice the programmed word length of the data.

7.3.13.1.2 Left-Justified Mode

The audio interface of the TLV320AIC3110 can enter the left-justified mode by programming page 0 / register 27, bits D7–D6 = 11. In left-justified mode, the MSB of the right channel is valid on the rising edge of the bit clock following the falling edge of the word clock. Similarly, the MSB of the left channel is valid on the rising edge of the bit clock following the rising edge of the word clock.

Figure 7-40 Timing Diagram for Left-Justified Mode

Figure 7-41 Timing Diagram for Left-Justified Mode With Offset = 1

Figure 7-42 Timing Diagram for Left-Justified Mode With Offset = 0 and Inverted Bit Clock

For the left-justified mode, the number of bit clocks per frame should be greater-than or equal-to twice the programmed word length of the data. Also, the programmed offset value should be less than the number of bit clocks per frame by at least the programmed word length of the data.

7.3.13.1.3 I²S Mode

The audio interface of the TLV320AIC3110 device enters I²S mode by programming page 0 / register 27, bits D7–D6 = to 00. In I²S mode, the MSB of the left channel is valid on the second rising edge of the bit clock after the falling edge of the word clock. Similarly, the MSB of the right channel is valid on the second rising edge of the bit clock after the rising edge of the word clock.

Figure 7-43 Timing Diagram for I²S Mode

Figure 7-44 Timing Diagram for I²S Mode With Offset = 2

Figure 7-45 Timing Diagram for I²S Mode With Offset = 0 and Bit Clock Inverted

For I²S mode, the number of bit clocks per channel should be greater-than or equal-to the programmed word length of the data. Also, the programmed offset value should be less than the number of bit clocks per frame by at least the programmed word length of the data.

Figure 7-46 shows the timing diagram for I²S mode for the monaural audio ADC.

Figure 7-46 Timing Diagram for I²S Mode for Monaural Audio ADC

7.3.13.1.4 DSP Mode

The audio interface of the TLV320AIC3110 can enter DSP mode by programming page 0 / register 27, bits D7–D6 = 01. In DSP mode, the falling edge of the word clock starts the data transfer with the left-channel data first and immediately followed by the right-channel data. Each data bit is valid on the falling edge of the bit clock.

Figure 7-47 Timing Diagram for DSP Mode

Figure 7-48 Timing Diagram for DSP Mode With Offset = 1

Figure 7-49 Timing Diagram for DSP Mode With Offset = 0 and Bit Clock Inverted

For the DSP mode, the number of bit clocks per frame should be greater-than or equal-to twice the programmed word length of the data. Also, the programmed offset value should be less than the number of bit clocks per frame by at least the programmed word length of the data.

7.3.13.2 Primary and Secondary Digital Audio Interface Selection

The audio serial interface on the TLV320AIC3110 has extensive I/O control to allow communication with two independent processors for audio data. The processors can communicate with the device one at a time. This feature is enabled by register programming of the various pin selections. Table 7-43 shows the primary and secondary audio interface selection and registers. Table 7-44 shows the selection criteria for generating ADC_WCLK. Figure 7-50 is a high-level diagram showing the general signal flow and multiplexing for the primary and secondary audio interfaces. For detailed information, see Table 7-43, Table 7-44, and the register definitions in .

Figure 7-50 Audio Serial Interface Multiplexing

7.3.13.3 Control Interface

The TLV320AIC3110 control interface supports the I²C communication protocol.

7.3.13.3.1 I²C Control Mode

The TLV320AIC3110 supports the I²C control protocol, and responds to the I²C address of 0011 000. I²C is a two-wire, open-drain interface supporting multiple devices and masters on a single bus. Devices on the I²C bus only drive the bus lines LOW by connecting them to ground; they never drive the bus lines HIGH. Instead, the bus wires are pulled HIGH by pullup resistors, so the bus wires are HIGH when no device is driving them LOW. This way, two devices cannot conflict; if two devices drive the bus simultaneously, there is no driver contention.

Communication on the I²C bus always takes place between two devices, one acting as the master and the other acting as the slave. Both masters and slaves can read and write, but slaves can only do so under the direction of the master. Some I²C devices can act as masters or slaves, but the TLV320AIC3110 can only act as a slave device.

An I²C bus consists of two lines, SDA and SCL. SDA carries data, and the SCL signal provides the clock. All data is transmitted across the I²C bus in groups of eight bits. To send a bit on the I²C bus, the SDA line is driven to the appropriate level while SCL is LOW (a LOW on SDA indicates the bit is zero, while a HIGH indicates the bit is one).

Once the SDA line has settled, the SCL line is brought HIGH, then LOW. This pulse on the SCL line clocks the SDA bit into the receiver shift register.

The I²C bus is bidirectional: the SDA line is used both for transmitting and receiving data. When a master reads from a slave, the slave drives the data line; when a master sends to a slave, the master drives the data line.

Most of the time the bus is idle, no communication is taking place, and both lines are HIGH. When communication is taking place, the bus is active. Only master devices can start communication on the bus. Generally, the data line is only allowed to change state while the clock line is LOW. If the data line changes state while the clock line is HIGH, it is either a START condition or the counterpart, a STOP condition. A START condition is when the clock line is HIGH and the data line goes from HIGH to LOW. A STOP condition is when the clock line is HIGH and the data line goes from LOW to HIGH.

After the master issues a START condition, it sends a byte that selects the slave device for communication. This byte is called the address byte. Each device on an I²C bus has a unique 7-bit address to which it responds. (Slaves can also have 10-bit addresses; see the I²C specification for details.) The master sends an address in the address byte, together with a bit that indicates whether it is to read from or write to the slave device.

Every byte transmitted on the I²C bus, whether it is address or data, is acknowledged with an acknowledge bit. When a master has finished sending a byte (eight data bits) to a slave, it stops driving SDA and waits for the slave to acknowledge the byte. The slave acknowledges the byte by pulling SDA LOW. The master then sends a clock pulse to clock the acknowledge bit. Similarly, when a master has finished reading a byte, it pulls SDA LOW to acknowledge this to the slave. It then sends a clock pulse to clock the bit. (Remember that the master always drives the clock line.)

A not-acknowledge is performed by simply leaving SDA HIGH during an acknowledge cycle. If a device is not present on the bus, and the master attempts to address the device, the master receives a not-acknowledge because no device is present at that address to pull the line LOW.

When a master has finished communicating with a slave, it may issue a STOP condition. When a STOP condition is issued, the bus becomes idle again. A master may also issue another START condition. When a START condition is issued while the bus is active, it is called a repeated START condition.

The TLV320AIC3110 can also respond to and acknowledge a general call, which consists of the master issuing a command with a slave address byte of 00h. This feature is disabled by default, but can be enabled through page 0 / register 34, bit D5.

Figure 7-51 I²C Write

Figure 7-52 I²C Read

In the case of an I²C register write, if the master does not issue a STOP condition, then the device enters auto-increment mode. So in the next eight clocks, the data on SDA is treated as data for the next incremental register.

Similarly, in the case of an I²C register read, after the device has sent out the 8-bit data from the addressed register, if the master issues a ACKNOWLEDGE, the slave takes over control of the SDA bus and transmits for the next eight clocks the data of the next incremental register.

Table 7-45 Summary of Register Map

7.4.2.1 Control Registers, Page 0 (Default Page): Clock Multipliers, Dividers, Serial Interfaces, Flags, Interrupts, and GPIOs