JAJSHF9E September   2008  – September 2019 TLV320AIC3204

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      ブロック概略図
  4. 4 改訂履歴
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics, ADC
    6. 7.6  Electrical Characteristics, Bypass Outputs
    7. 7.7  Electrical Characteristics, Microphone Interface
    8. 7.8  Electrical Characteristics, Audio DAC Outputs
    9. 7.9  Electrical Characteristics, LDO
    10. 7.10 Electrical Characteristics, Misc.
    11. 7.11 Electrical Characteristics, Logic Levels
    12. 7.12 I2S LJF and RJF Timing in Master Mode (see )
    13. 7.13 I2S LJF and RJF Timing in Slave Mode (see )
    14. 7.14 DSP Timing in Master Mode (see )
    15. 7.15 DSP Timing in Slave Mode (see )
    16. 7.16 Digital Microphone PDM Timing (see )
    17. 7.17 I2C Interface Timing
    18. 7.18 SPI Interface Timing (See )
    19. 7.19 Typical Characteristics
    20. 7.20 Typical Characteristics, FFT
  8. 8 Parameter Measurement Information
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Device Connections
        1. 9.3.1.1 Digital Pins
          1. 9.3.1.1.1 Multifunction Pins
        2. 9.3.1.2 Analog Pins
      2. 9.3.2 Analog Audio IO
        1. 9.3.2.1 Analog Low Power Bypass
        2. 9.3.2.2 ADC Bypass Using Mixer Amplifiers
        3. 9.3.2.3 Headphone Outputs
        4. 9.3.2.4 Line Outputs
      3. 9.3.3 ADC
        1. 9.3.3.1 ADC Processing
          1. 9.3.3.1.1 ADC Processing Blocks
      4. 9.3.4 DAC
        1. 9.3.4.1 DAC Processing Blocks
      5. 9.3.5 PowerTune
      6. 9.3.6 Digital Audio IO Interface
      7. 9.3.7 Clock Generation and PLL
      8. 9.3.8 Control Interfaces
        1. 9.3.8.1 I2C Control
        2. 9.3.8.2 SPI Control
    4. 9.4 Device Functional Modes
    5. 9.5 Register Map
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
        1. 10.2.1.1 Reference Filtering Capacitor
        2. 10.2.1.2 MICBIAS
      2. 10.2.2 Detailed Design Procedures
        1. 10.2.2.1 Analog Input Connection
        2. 10.2.2.2 Analog Output Connection
      3. 10.2.3 Application Curves
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13デバイスおよびドキュメントのサポート
    1. 13.1 ドキュメントのサポート
      1. 13.1.1 関連資料
    2. 13.2 ドキュメントの更新通知を受け取る方法
    3. 13.3 コミュニティ・リソース
    4. 13.4 商標
    5. 13.5 静電気放電に関する注意事項
    6. 13.6 Glossary
  14. 14メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.8 Electrical Characteristics, Audio DAC Outputs

At 25°C, AVDD, DVDD, IOVDD = 1.8V, LDOIN = 3.3V, AVDD and DVDD LDO disabled, fs (Audio) = 48kHz, Cref = 10µF on REF pin, PLL disabled unless otherwise noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
AUDIO DAC – STEREO SINGLE-ENDED LINE OUTPUT
Device Setup Load = 10kΩ (single-ended), 56pF
Line Output on AVDD Supply
Input and Output CM = 0.9V
DOSR = 128, MCLK = 256 x fs,
Channel Gain = 0dB, word length = 16 bits,
Processing Block = PRB_P1,
Power Tune = PTM_P3
Full scale output voltage (0dB) 0.5 VRMS
SNR Signal-to-noise ratio A-weighted(1)(2) All zeros fed to DAC input 87 100 dB
DR Dynamic range, A-weighted(1)(2) –60dB 1kHz input full-scale signal, Word length = 20 bits 100 dB
THD+N Total Harmonic Distortion plus Noise –3dB full-scale, 1kHz input signal –83 –70 dB
DAC Gain Error 0 dB, 1kHz input full scale signal 0.3 dB
DAC Mute Attenuation Mute 119 dB
DAC channel separation –1 dB, 1kHz signal, between left and right HP out 113 dB
DAC PSRR 100mVpp, 1kHz signal applied to AVDD 73 dB
100mVpp, 217Hz signal applied to AVDD 77 dB
AUDIO DAC – STEREO SINGLE-ENDED LINE OUTPUT
Device Setup Load = 10kΩ (single-ended), 56pF
Line Output on AVDD Supply
Input and Output CM = 0.75V; AVDD = 1.5V
DOSR = 128
MCLK = 256 * fs
Channel Gain = –2dB
word length = 20 bits
Processing Block = PRB_P1
Power Tune = PTM_P4
Full scale output voltage (0dB) 0.375 VRMS
SNR Signal-to-noise ratio, A-weighted(1)(2) All zeros fed to DAC input 99 dB
DR Dynamic range, A-weighted(1)(2) –60dB 1 kHz input full-scale signal 97 dB
THD+N Total Harmonic Distortion plus Noise –1 dB full-scale, 1-kHz input signal –85 dB
AUDIO DAC – STEREO SINGLE-ENDED HEADPHONE OUTPUT
Device Setup Load = 16Ω (single-ended), 50pF
Headphone Output on AVDD Supply,
Input and Output CM = 0.9V, DOSR = 128,
MCLK = 256 * fs, Channel Gain = 0dB
word length = 16 bits;
Processing Block = PRB_P1
Power Tune = PTM_P3
Full scale output voltage (0dB) 0.5 VRMS
SNR Signal-to-noise ratio, A-weighted(1)(2) All zeros fed to DAC input 87 100 dB
DR Dynamic range, A-weighted(1)(2) –60dB 1kHz input full-scale signal, Word Length = 20 bits, Power Tune = PTM_P4 99 dB
THD+N Total Harmonic Distortion plus Noise –3dB full-scale, 1kHz input signal –83 –70 dB
DAC Gain Error 0dB, 1kHz input full scale signal –0.3 dB
DAC Mute Attenuation Mute 122 dB
DAC channel separation –1dB, 1kHz signal, between left and right HP out 110 dB
DAC PSRR 100mVpp, 1kHz signal applied to AVDD 73 dB
100mVpp, 217Hz signal applied to AVDD 78 dB
Power Delivered RL = 16Ω, Output Stage on AVDD = 1.8V
THDN < 1%, Input CM = 0.9V,
Output CM = 0.9V		 15 mW
RL = 16Ω Output Stage on LDOIN = 3.3V,
THDN < 1% Input CM = 0.9V,
Output CM = 1.65V		 64
AUDIO DAC – STEREO SINGLE-ENDED HEADPHONE OUTPUT
Device Setup Load = 16Ω (single-ended), 50pF,
Headphone Output on AVDD Supply,
Input and Output CM = 0.75V; AVDD = 1.5V,
DOSR = 128, MCLK = 256 * fs,
Channel Gain = –2dB, word length = 20-bits;
Processing Block = PRB_P1,
Power Tune = PTM_P4
Full scale output voltage (0dB) 0.375 VRMS
SNR Signal-to-noise ratio, A-weighted(1)(2) All zeros fed to DAC input 99 dB
DR Dynamic range, A-weighted(1)(2) -60dB 1kHz input full-scale signal 98 dB
THD+N Total Harmonic Distortion plus Noise –1dB full-scale, 1kHz input signal –83 dB
AUDIO DAC – MONO DIFFERENTIAL HEADPHONE OUTPUT
Device Setup Load = 32Ω (differential), 50pF,
Headphone Output on LDOIN Supply
Input CM = 0.75V, Output CM = 1.5V,
AVDD = 1.8V, LDOIN = 3.0V, DOSR = 128
MCLK = 256 * fs, Channel (headphone driver) Gain = 5dB for full scale output signal,
word length = 16 bits,
Processing Block = PRB_P1,
Power Tune = PTM_P3
Full scale output voltage (0dB) 1778 mVRMS
SNR Signal-to-noise ratio, A-weighted(1)(2) All zeros fed to DAC input 98 dB
DR Dynamic range, A-weighted(1)(2) –60dB 1kHz input full-scale signal 96 dB
THD Total Harmonic Distortion –3dB full-scale, 1kHz input signal –82 dB
Power Delivered RL = 32Ω, Output Stage on LDOIN = 3.3V,
THDN < 1%, Input CM = 0.9V,
Output CM = 1.65V		 136 mW
RL = 32Ω Output Stage on LDOIN = 3.0V,
THDN < 1% Input CM = 0.9V,
Output CM = 1.5V		 114 mW
(1) Ratio of output level with 1kHz full-scale sine wave input, to the output level with the inputs short circuited, measured A-weighted over a 20Hz to 20kHz bandwidth using an audio analyzer.
(2) All performance measured with 20kHz low-pass filter and, where noted, A-weighted filter. Testing without such a filter may result in higher THD+N and lower SNR and dynamic range readings than shown in the Electrical Characteristics. The low-pass filter removes out-of-band noise, which, although not audible, may affect dynamic specification values