JAJSHF9E September   2008  – September 2019 TLV320AIC3204

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      ブロック概略図
  4. 4 改訂履歴
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics, ADC
    6. 7.6  Electrical Characteristics, Bypass Outputs
    7. 7.7  Electrical Characteristics, Microphone Interface
    8. 7.8  Electrical Characteristics, Audio DAC Outputs
    9. 7.9  Electrical Characteristics, LDO
    10. 7.10 Electrical Characteristics, Misc.
    11. 7.11 Electrical Characteristics, Logic Levels
    12. 7.12 I2S LJF and RJF Timing in Master Mode (see )
    13. 7.13 I2S LJF and RJF Timing in Slave Mode (see )
    14. 7.14 DSP Timing in Master Mode (see )
    15. 7.15 DSP Timing in Slave Mode (see )
    16. 7.16 Digital Microphone PDM Timing (see )
    17. 7.17 I2C Interface Timing
    18. 7.18 SPI Interface Timing (See )
    19. 7.19 Typical Characteristics
    20. 7.20 Typical Characteristics, FFT
  8. 8 Parameter Measurement Information
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Device Connections
        1. 9.3.1.1 Digital Pins
          1. 9.3.1.1.1 Multifunction Pins
        2. 9.3.1.2 Analog Pins
      2. 9.3.2 Analog Audio IO
        1. 9.3.2.1 Analog Low Power Bypass
        2. 9.3.2.2 ADC Bypass Using Mixer Amplifiers
        3. 9.3.2.3 Headphone Outputs
        4. 9.3.2.4 Line Outputs
      3. 9.3.3 ADC
        1. 9.3.3.1 ADC Processing
          1. 9.3.3.1.1 ADC Processing Blocks
      4. 9.3.4 DAC
        1. 9.3.4.1 DAC Processing Blocks
      5. 9.3.5 PowerTune
      6. 9.3.6 Digital Audio IO Interface
      7. 9.3.7 Clock Generation and PLL
      8. 9.3.8 Control Interfaces
        1. 9.3.8.1 I2C Control
        2. 9.3.8.2 SPI Control
    4. 9.4 Device Functional Modes
    5. 9.5 Register Map
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
        1. 10.2.1.1 Reference Filtering Capacitor
        2. 10.2.1.2 MICBIAS
      2. 10.2.2 Detailed Design Procedures
        1. 10.2.2.1 Analog Input Connection
        2. 10.2.2.2 Analog Output Connection
      3. 10.2.3 Application Curves
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13デバイスおよびドキュメントのサポート
    1. 13.1 ドキュメントのサポート
      1. 13.1.1 関連資料
    2. 13.2 ドキュメントの更新通知を受け取る方法
    3. 13.3 コミュニティ・リソース
    4. 13.4 商標
    5. 13.5 静電気放電に関する注意事項
    6. 13.6 Glossary
  14. 14メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

10.2.2.1 Analog Input Connection

The analog inputs to TLV320AIC3204 should be ac-coupled to the device terminals to allow decoupling of signal source's common mode voltage with that of TLV320AIC3204's common mode voltage. The input coupling capacitor in combination with the selected input impedance of TLV320AIC3204 forms a high-pass filter.

Equation 1. Fc = 1/(2 x π x ReqCc)
Equation 2. Cc = 1/(2 x π x ReqFc)

For high fidelity audio recording application it is desirable to keep the cutoff frequency of the high pass filter as low as possible. For single-ended input mode, the equivalent input resistance Req can be calculated as

Equation 3. Req = Rin x (1 + 2g)/(1+g)

where g is the analog PGA gain calculated in linear terms.

Equation 4. g = 10000 x 2floor(G/6)/Rin

where G is the analog PGA gain programmed in P1_R59-R60 (in dB) and Rin is the value of the resistor programmed in P1_R52-R57 and assumes Rin = Rcm (as defined in P1_R52-R57).

For differential input mode, Req of the half circuit can be calculated as:

Equation 5. Req = Rin

where Rin is the value of the resistor programmed in P1_R52-R57, assuming symmetrical inputs.

TLV320AIC3204 aic3268_schem_app_ana_in_1r.gifFigure 22. Analog Input Connection With Pull-down Resistor

When the analog signal is connected to the system through a connector such as audio jack, it is recommended to put a pull-down resistor on the signal as shown in Figure 22. The pulldown resistor helps keep the signal grounded and helps improve noise immunity when no source is connected to the connector. The pulldown resistor value should be chosen large enough to avoid loading of signal source.

Each analog input of the TLV320AIC3204 is capable of handling signal amplitude of 0.5 Vrms. If the input signal source can drive signals higher than the maximum value, an external resistor divider network as shown in Figure 23 should be used to attenuate the signal to less than 0.5Vrms before connecting the signal to the device. The resistor values of the network should be chosen to provide desired attenuation as well as Equation 6.

Equation 6. R1|| R2<< Req
TLV320AIC3204 aic3268_schem_app_ana_in_2r.gifFigure 23. Analog Input Connection With Resistor Divider Network

Whenever any of the analog input terminals IN1_L, IN2_L, IN3_L, IN1_R, IN2_R or IN3_R are not used in an application, it is recommended to short the unused input terminals together (if convenient) and connect them to ground using a small capacitor (example 0.1 µF).