SNOSDK3 September   2024 TLV3603-EP

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Diagrams
    7. 5.7 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
    4. 6.4 Device Functional Modes
      1. 6.4.1 Inputs
      2. 6.4.2 Push-Pull (Single-Ended) Output
      3. 6.4.3 Known Startup Condition
  8. 7 Application and Implementation
    1. 7.1 Application Information
      1. 7.1.1 Adjustable Hysteresis
      2. 7.1.2 Capacitive Loads
      3. 7.1.3 Latch Functionality
    2. 7.2 Typical Application
      1. 7.2.1 Implementing Adjustable Hysteresis
        1. 7.2.1.1 Design Requirements
        2. 7.2.1.2 Detailed Design Procedure
        3. 7.2.1.3 Application Curve
      2. 7.2.2 Optical Receiver
      3. 7.2.3 Over-Current Latch Condition
  9. 8 Power Supply Recommendations
  10. 9 Layout
    1. 9.1 Layout Guidelines
    2. 9.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 Development Support
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

5.5 Electrical Characteristics

VCC = 2.5, 3.3 and 5V, VEE = 0V, VCM = VEE + 300mV, CL = 5pF probe capacitance, typical at TA = 25°C (unless otherwise noted).
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
DC Input Characteristics 
VIO Input offset voltage TA = –55°C to +125℃  -7 ±0.5 7 mV
dVIO/dT Input offset voltage drift ±3.0 μV/°C
VCM Input common mode voltage range TA = –55℃ to +125℃ VEE – 0.2 VCC + 0.2 V
CIN Input capacitance 1 pF
RDM Input differential mode resistance 67 kΩ
RCM Input common mode resistance 5 MΩ
IB Input bias current TA = –55℃ to +125℃ 1 5 uA
IOS Input offset current ±0.03 uA
CMRR Common-mode rejection ratio VCM = VEE – 0.2V to VCC + 0.2V 80 dB
PSRR Power-supply rejection ratio VCC = 2.4 to 5.5V 80 dB
DC Output Characteristics
VOH Output high voltage from VCC ISOURCE = 1mA
TA = –55℃ to +125℃		 60 80 mV
VOL Output low voltage from VEE ISINK = 1mA
TA = –55℃ to +125℃		 60 80 mV
ISC_SOURCE  Output Short-Circuit Current - Source TA = –55℃ to +125℃ 10 30 mA
ISC_SINK Output Short-Circuit Current - Sink TA = –55℃ to +125℃ 10 30 mA
Power Supply
ICC quiescent current Output being high
TA = –55℃ to +125℃		 5.7 7.8 mA
VPOR (postive) Power-On Reset Voltage 2.1 V
AC Characteristics
tPD Propagation delay VOVERDRIVE = VUNDERDRIVE = 50mV
TA = –55℃ to +125℃		 2.5 4.5(1) ns
tCM_DISPERSION Common dispersion VCM varied from VEE  to VCC   80 ps
tOD_DISPERSION Overdrive dispersion Overdrive varied from 10mV to 125mV 700 ps
tUD_DISPERSION Underdrive dispersion Underdrive varied from 10mV to 125mV 330 ps
tR Rise time 10% to 90% 0.75 ns
tF Fall time 90% to 10% 0.75 ns
tJITTER RMS Jitter VIN = 100mVP-P,
fIN = 100MHz, Jitter BW = 10Hz – 50MHz		 4 ps
fTOGGLE Input toggle frequency VIN = 200mVPP Sine Wave,
When output high reaches 90% of VCC - VEE or output low reaches 10% of VCC - VEE		 325 MHz
PulseWidth Minimum allowed input pulse width VOVERDRIVE = VUNDERDRIVE = 50mV
PWOUT = 90% of PWIN		 1.5 ns
Latching/Adjustable Hysteresis
VHYST Input hysteresis voltage VHYST = Logic High 0 mV
VHYST Input hysteresis voltage RHYST = Floating 3 mV
VHYST Input hysteresis voltage RHYST = 150kΩ 30 mV
VHYST Input hysteresis voltage RHYST = 56kΩ 60 mV
VIH_LE LE pin input high level TA = –55℃ to +125℃ VEE + 1.5 V
VIL_LE LE pin input low level TA = –55℃ to +125℃ VEE + 0.35 V
IIH_LE LE pin input leakage current VLE = VCC
TA = –55℃ to +125℃		 15 uA
IIL_LE LE pin input leakage current VLE = VEE,
TA = –55℃ to +125℃		 40 uA
tSETUP Latch setup time –1.4 ns
tHOLD Latch hold time 7.2 ns
tPL Latch to OUT delay 7 ns
(1) Assured by characterization