JAJSCL5C November   2016  – January 2019 TLV172 , TLV2172 , TLV4172

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     概略回路図
  4. 4 改訂履歴
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
    1.     Pin Functions: TLV172
    2.     Pin Functions: TLV2172
    3.     Pin Functions: TLV4172
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information: TLV172
    5. 7.5 Thermal Information: TLV2172
    6. 7.6 Thermal Information: TLV4172
    7. 7.7 Electrical Characteristics
    8. 7.8 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Operating Characteristics
      2. 8.3.2 Phase-Reversal Protection
      3. 8.3.3 Electrical Overstress
      4. 8.3.4 Capacitive Load and Stability
    4. 8.4 Device Functional Modes
      1. 8.4.1 Common-Mode Voltage Range
      2. 8.4.2 Overload Recovery
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curve
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12デバイスおよびドキュメントのサポート
    1. 12.1 デバイス・サポート
      1. 12.1.1 デベロッパー・ネットワークの製品に関する免責事項
      2. 12.1.2 開発サポート
        1. 12.1.2.1 TINA-TI™ (無料のダウンロード・ソフトウェア)
        2. 12.1.2.2 DIPアダプタ評価モジュール
        3. 12.1.2.3 ユニバーサル・オペアンプ評価基板
        4. 12.1.2.4 TI Precision Designs
        5. 12.1.2.5 WEBENCH Filter Designer
    2. 12.2 ドキュメントのサポート
      1. 12.2.1 関連資料
    3. 12.3 関連リンク
    4. 12.4 ドキュメントの更新通知を受け取る方法
    5. 12.5 コミュニティ・リソース
    6. 12.6 商標
    7. 12.7 静電気放電に関する注意事項
    8. 12.8 Glossary
  13. 13メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.7 Electrical Characteristics

at TA = 25°C, VS = ±2.25 V to ±18 V, VCM = VOUT = VS / 2, and RL = 10 kΩ connected to VS / 2 (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
OFFSET VOLTAGE
VOS Input offset voltage TA = 25°C 0.5 1.7 mV
TA = –40°C to +125°C 2
dVOS/dT Input offset voltage drift TA = –40°C to +125°C 1 µV/°C
PSRR Power-supply rejection ratio VS = 4 V to 36 V, TA = –40°C to +125°C 100 120 dB
Channel separation, dc 5 µV/V
INPUT BIAS CURRENT
IB Input bias current TA = 25°C ±10 pA
IOS Input offset current TA = 25°C ±2 pA
NOISE
Input voltage noise f = 0.1 Hz to 10 Hz 2.5 µVPP
en Input voltage noise density f = 100 Hz 14 nV/√Hz
f = 1 kHz 9 nV/√Hz
in Input current noise density f = 1 kHz 1.6 fA/√Hz
INPUT VOLTAGE
VCM Common-mode voltage range(1) (V–) – 0.1 (V+) – 2 V
CMRR Common-mode rejection ratio VS = ±18 V, (V–) – 0.1 V < VCM < (V+) – 2 V,
TA = –40°C to +125°C		 94 116 dB
INPUT IMPEDANCE
Differential 100 || 4 MΩ || pF
Common-mode 6 || 4 1013 Ω || pF
OPEN-LOOP GAIN
AOL Open-loop voltage gain (V–) + 0.35 V < VO < (V+) – 0.35 V, TA = –40°C to +125°C 97 115 dB
(V–) + 0.5 V < VO < (V+) – 0.5 V,
RL = 2 kΩ, TA = –40°C to +125°C		 107
FREQUENCY RESPONSE
GBP Gain bandwidth product 10 MHz
SR Slew rate G = +1 10 V/µs
tS Settling time To 0.1%, VS = ±18 V, G = +1, 10-V step 2 µs
To 0.01% (12-bit), VS = ±18 V, G = +1, 10-V step 3.2
Overload recovery time VIN × gain > VS 200 ns
THD+N Total harmonic distortion + noise VS = 36 V, G = +1, f = 1 kHz, VO = 3.5 VRMS 0.0002%
OUTPUT
VO Voltage output swing from rail VS = ±18 V, RL = 10 kΩ TA = 25°C 70 mV
TA = –40°C to +125°C 95
VS = ±18 V, RL = 2 kΩ TA = 25°C 330 400
TA = –40°C to +125°C 470 530
ISC Short-circuit current ±75 mA
CLOAD Capacitive load drive See Typical Characteristics pF
RO Open-loop output resistance f = 1 MHz, IO = 0 A 60 Ω
POWER SUPPLY
VS Specified voltage range 4.5 36 V
IQ Quiescent current per amplifier IO = 0 A, TA = –40°C to +125°C 1.6 2.3 mA
(1) The input range can be extended beyond (V+) – 2 V up to V+. See the Typical Characteristics and Application and Implementation sections for additional information.