JAJSBR5H February   2012  – June 2018 TLV62130 , TLV62130A

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      代表的なアプリケーションの回路図
      2.      効率と出力電流との関係
  4. 4 改訂履歴
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Enable / Shutdown (EN)
      2. 8.3.2 Soft Start / Tracking (SS/TR)
      3. 8.3.3 Power Good (PG)
      4. 8.3.4 Pin-Selectable Output Voltage (DEF)
      5. 8.3.5 Frequency Selection (FSW)
      6. 8.3.6 Undervoltage Lockout (UVLO)
      7. 8.3.7 Thermal Shutdown
    4. 8.4 Device Functional Modes
      1. 8.4.1 Pulse Width Modulation (PWM) Operation
      2. 8.4.2 Power Save Mode Operation
      3. 8.4.3 100% Duty-Cycle Operation
      4. 8.4.4 Current Limit and Short Circuit Protection
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Custom Design With WEBENCH® Tools
        2. 9.2.2.2 Programming the Output Voltage
        3. 9.2.2.3 External Component Selection
          1. 9.2.2.3.1 Inductor Selection
          2. 9.2.2.3.2 Capacitor Selection
            1. 9.2.2.3.2.1 Output Capacitor
            2. 9.2.2.3.2.2 Input Capacitor
            3. 9.2.2.3.2.3 Soft Start Capacitor
        4. 9.2.2.4 Tracking Function
        5. 9.2.2.5 Output Filter and Loop Stability
      3. 9.2.3 Application Curves
    3. 9.3 System Examples
      1. 9.3.1 LED Power Supply
      2. 9.3.2 Active Output Discharge
      3. 9.3.3 Inverting Power Supply
      4. 9.3.4 Various Output Voltages
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
    3. 11.3 Thermal Considerations
  12. 12デバイスおよびドキュメントのサポート
    1. 12.1 デバイス・サポート
      1. 12.1.1 デベロッパー・ネットワークの製品に関する免責事項
      2. 12.1.2 開発サポート
        1. 12.1.2.1 WEBENCH®ツールによるカスタム設計
    2. 12.2 ドキュメントの更新通知を受け取る方法
    3. 12.3 ドキュメントのサポート
      1. 12.3.1 関連資料
    4. 12.4 関連リンク
    5. 12.5 コミュニティ・リソース
    6. 12.6 商標
    7. 12.7 静電気放電に関する注意事項
    8. 12.8 Glossary
  13. 13メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.5 Electrical Characteristics

over operating free-air temperature range (TA = -40°C to +85°C), typical values at VIN = 12 V and TA = 25°C (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
POWER SUPPLY
VIN Input Voltage Range(1) 3 17 V
IQ Operating Quiescent Current EN=High, IOUT = 0 mA, device not switching 19 27 μA
ISD Shutdown Current (2) EN=Low 1.5 4 μA
VUVLO Undervoltage Lockout Threshold Falling Input Voltage (PWM mode operation) 2.6 2.7 2.8 V
Hysteresis 200 mV
TSD Thermal Shutdown Temperature 160 °C
Thermal Shutdown Hysteresis 20
CONTROL (EN, DEF, FSW, SS/TR, PG)
VH High Level Input Threshold Voltage (EN, DEF, FSW) 0.9 V
VL Low Level Input Threshold Voltage (EN, DEF, FSW) 0.3 V
ILKG Input Leakage Current (EN, DEF, FSW) EN = VIN or GND; DEF, FSW = VOUT or GND 0.01 1 μA
VTH_PG Power Good Threshold Voltage Rising (%VOUT) 92% 95% 98%
Falling (%VOUT) 87% 90% 94%
VOL_PG Power Good Output Low IPG = -2 mA 0.07 0.3 V
ILKG_PG Input Leakage Current (PG) VPG = 1.8 V 1 400 nA
ISS/TR SS/TR Pin Source Current 2.3 2.5 2.7 μA
POWER SWITCH
RDS(ON) High-Side MOSFET ON-Resistance VIN ≥ 6 V 90 mΩ
Low-Side MOSFET ON-Resistance VIN ≥ 6 V 40 mΩ
ILIMF High-Side MOSFET Forward Current Limit(3) VIN = 12 V, TA = 25°C 3.6 4.2 A
OUTPUT
ILKG_FB Input Leakage Current (FB) VFB = 0.8 V 1 100 nA
VOUT Output Voltage Range VIN ≥ VOUT 0.9 5.5 V
DEF (Output Voltage Programming) DEF=0 (GND) VOUT
DEF=1 (VOUT) VOUT+5%
Initial Output Voltage Accuracy(4) PWM mode operation, VIN ≥ VOUT +1 V 780 800 820 mV
Load Regulation(5) VIN = 12 V, VOUT = 3.3 V, PWM mode operation 0.05 %/A
Line Regulation(5) 4 V ≤ VIN ≤ 17 V, VOUT = 3.3 V, IOUT = 1 A, PWM mode operation 0.02 %/V
(1) The device is still functional down to Undervoltage Lockout (see parameter VUVLO).
(2) Current into AVIN + PVIN pin.
(3) This is the static current limit. It can be temporarily higher in applications due to internal propagation delay (see Current Limit and Short Circuit Protection).
(4) This is the accuracy provided at the FB pin (line and load regulation effects are not included).
(5) Line and load regulation depend on external component selection and layout (see Figure 20 and Figure 21).