JAJSEJ9B January 2018 – October 2018 TLV6710
PRODUCTION DATA.
In a typical TLV6710 application, the outputs are connected to a GPIO input of the processor (such as a digital signal processor [DSP], central processing unit [CPU], field-programmable gate array [FPGA], or application-specific integrated circuit [ASIC]).
The TLV6710 provides two open-drain outputs (OUTA and OUTB); use pullup resistors to hold these lines high when the output goes to a high-impedance state. Connect pullup resistors to the proper voltage rails to enable the outputs to be connected to other devices at correct interface voltage levels. The TLV6710 outputs can be pulled up to 25 V, independent of the device supply voltage. To ensure proper voltage levels, give some consideration when choosing the pullup resistor values. The pullup resistor value is determined by VOL, output capacitive loading, and output leakage current (ID(leak)). These values are specified in the Electrical Characteristicstable. Use wired-OR logic to merge OUTA and OUTB into one logic signal.
Table 2 and the Inputs (INA, INB) section describe how the outputs are asserted or high impedance. See Figure 1 for a timing diagram that describes the relationship between threshold voltages and the respective output.