TLV700xx-Q1 200-mA Low-IQ Low-Dropout Regulator for Portable Devices
1 Features
- Qualified for Automotive Applications
- AEC-Q100 Qualified With the Following Results:
- 2% Accuracy
- Low IQ: 31 μA
- Fixed Output Voltages
- High PSRR: 68 dB at 1 kHz
- Stable With Effective Capacitance of 0.1 μF
- Thermal Shutdown and Overcurrent Protection
- Latch-Up Performance Meets 100 mA
Per AEC-Q100, Level I - Available in the SOT-5 (DDC) and SC70-5 (DCK) Packages
3 Description
The TLV700xx-Q1 family of low-dropout (LDO) linear regulators are low-quiescent-current devices with excellent line- and load-transient performance. These LDOs are designed for power-sensitive applications. A precision band-gap and error amplifier provides overall 2% accuracy. Low output noise, very high power-supply rejection ratio (PSRR), and low dropout voltage make this series of devices ideal for most battery-operated handheld equipment or for working as a second-stage power supply for connecting automotive battery applications. All device versions have thermal shutdown and current limit for safety.
Furthermore, these devices are stable with an effective output capacitance of only 0.1 μF. This feature enables the use of cost-effective capacitors that have higher bias voltages and temperature derating. The devices regulate to specified accuracy with no output load.
The TLV700xx-Q1 LDOs are available in the SOT-5 (DDC) and the SC70-5 (DCK) packages.
Device Information(1)
| PART NUMBER | PACKAGE | BODY SIZE (NOM) |
|---|---|---|
| TLV70012A-Q1 | SC70 (5) | 2.00 mm × 1.25 mm |
| TLV70025-Q1 | SOT (5) | 2.90 mm × 1.60 mm |
| TLV70030-Q1 | SC70 (5) | 2.00 mm × 1.25 mm |
| TLV70033-Q1 | SOT (5) | 2.90 mm × 1.60 mm |
- For all available packages, see the orderable addendum at the end of the data sheet.
4 Revision History
Changes from G Revision (September 2015) to H Revision
- Deleted all occurences of TLV70028-Q1 and TLV70032-Q1 throughout the data sheetGo
- Added an I/O column to the Pin Functions table Go
- Added Recommended Operating Conditions table to the data sheetGo
- Moved "High-ESR capacitors..." sentence here from the former Board Layout Recommendations to Improve PSRR and Noise Performance section 8.1.2Go
- Deleted the Board Layout Recommendations to Improve PSRR and Noise Performance section. Moved its non-redundant contents to Input and Output Capacitor Requirements or Layout Guidelines, as appropriateGo
- Changed Z to R in the equations Go
- Moved some layout information here from former Sectioni 8.1.2, Board Layout Recommendations to Improve PSRR and Noise PerformanceGo
- Added the Receiving Notification of Documentation Updates sectionGo
Changes from F Revision (August 2013) to G Revision
- Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information sectionGo
Changes from E Revision (January 2013) to F Revision
- Changed CDM classification level from C3B to C4B in FEATURES listGo
- Changed Added TJ to the Absolute Maximum Ratings and moved TA to the Recommended Operating ConditionsGo
- Changed Ground pin current (shutdown) max value from 2 to 2.5 in Electrical Characteristics tableGo
- Added TLV70028-Q1 and TLV70032-Q1 to documentGo
5 Pin Configuration and Functions
Pin Functions
6 Specifications
6.1 Absolute Maximum Ratings
At TA = –40°C to 125°C (unless otherwise noted). All voltages are with respect to GND.(1)6.2 ESD Ratings
| VALUE | UNIT | |||
|---|---|---|---|---|
| V(ESD) | Electrostatic discharge | Human-body model (HBM), per AEC Q100-002(1) | ±2000 | V |
| Charged-device model (CDM), per AEC Q100-011 | ±750 | |||
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)| MIN | NOM | MAX | UNIT | ||
|---|---|---|---|---|---|
| VIN | Input supply-voltage range | 2 | 5.5 | V | |
| VOUT | Output voltage | 1.2 | 4.8 | V | |
| IOUT | Oytput current | 0 | 200 | mA | |
| VEN | Voltage on EN pin | 0 | VIN | V | |
| TA | Operating ambient temperature | –40 | 125 | °C | |
6.4 Thermal Information
| THERMAL METRIC(1) | TLV700xx-Q1 | UNIT | ||
|---|---|---|---|---|
| DCK (SOT) | DDC (SOT) | |||
| 5 Pins | 5 PINS | |||
| RθJA | Junction-to-ambient thermal resistance | 307.6 | 262.8 | °C/W |
| RθJC(top) | Junction-to-case (top) thermal resistance | 79.1 | 68.2 | °C/W |
| RθJB | Junction-to-board thermal resistance | 93.7 | 81.6 | °C/W |
| ψJT | Junction-to-top characterization parameter | 1.3 | 1.1 | °C/W |
| ψJB | Junction-to-board characterization parameter | 92.8 | 80.9 | °C/W |
| RθJC(bot) | Junction-to-case (bottom) thermal resistance | n/a | n/a | °C/W |
6.5 Electrical Characteristics
VIN = VOUT(TYP) + 0.3 V or 2 V (whichever is greater); IOUT = 10 mA, VEN = VIN, COUT = 1 μF, and TA = –40°C to 125°C (unless otherwise noted). Typical values are at TA = 25°C.space
| PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |||
|---|---|---|---|---|---|---|---|---|
| VOUT | DC output accuracy | –40°C ≤ TA ≤ 125°C | VOUT ≥ 1 V | –2% | 2% | |||
| VOUT < 1 V | –20 | 20 | mV | |||||
| ΔVO / ΔVIN | Line regulation | VOUT(NOM) + 0.5 V ≤ VIN ≤ 5.5 V IOUT = 10 mA |
1 | 5 | mV | |||
| ΔVO / ΔIOUT | Load regulation | 0 mA ≤ IOUT ≤ 200 mA, TLV70025-Q1 TLV70030-Q1, TLV70033-Q1 |
15 | mV | ||||
| 0 mA ≤ IOUT ≤ 200 mA, TLV70012A-Q1 | 20 | |||||||
| VDO | Dropout voltage(1) | VIN = 0.98 × VOUT(NOM), IOUT = 200 mA | 175 | 250 | mV | |||
| ICL | Output current limit | VOUT = 0.9 × VOUT(NOM) | 220 | 350 | 550 | mA | ||
| IGND | Ground pin current | IOUT = 0 mA | 31 | 55 | μA | |||
| IOUT = 200 mA, VIN = VOUT + 0.5 V | 270 | μA | ||||||
| ISHDN | Ground pin current (shutdown) | VEN ≤ 0.4 V, 2 V ≤ VIN ≤ 4.5 V | 1 | 2.5 | μA | |||
| PSRR | Power-supply rejection ratio | VIN = 2.3 V, VOUT = 1.8 V IOUT = 10 mA, f = 1 kHz |
68 | dB | ||||
| VN | Output noise voltage | BW = 100 Hz to 100 kHz VIN = 2.3 V, VOUT = 1.8 V, IOUT = 10 mA |
48 | μVRMS | ||||
| tSTR | Startup time(2) | COUT = 1 μF, IOUT = 200 mA | 100 | μs | ||||
| VEN(HI) | Enable pin high (enabled) | 0.9 | VIN | V | ||||
| VEN(LO) | Enable pin low (disabled) | 0 | 0.4 | V | ||||
| IEN | Enable pin current | VEN = 5.5 V , IOUT = 10 μA | 0.04 | 0.5 | μA | |||
| UVLO | Undervoltage lockout | VIN rising | 1.9 | V | ||||
| TSD | Thermal shutdown temperature | Shutdown, temperature increasing | 160 | °C | ||||
| Reset, temperature decreasing | 140 | °C | ||||||
| TA | Operating ambient temperature | –40 | 125 | °C | ||||
6.6 Typical Characteristics
TJ = –40°C to 125°C, VIN = VOUT(TYP) + 0.5 V or 2 V (whichever is greater); IOUT = 10 mA, VEN = VIN, COUT = 1 μF (unless otherwise noted). Typical values are at TJ = 25°C.
7 Detailed Description
7.1 Overview
The TLV700xx-Q1 low-dropout (LDO) linear regulators are low-quiescent-current devices with excellent line- and load-transient performance. These LDOs are designed for power-sensitive applications. A precision band-gap and error amplifier provides overall 2% accuracy together with low output noise, very high power-supply rejection ratio (PSRR), and low dropout voltage.
7.3 Feature Description
7.3.1 Internal Current Limit
The TLV700xx-Q1 internal current limit helps to protect the regulator during fault conditions. During current limit, the output sources a fixed amount of current that is largely independent of the output voltage. In such a case, the output voltage is not regulated, and is VOUT = ILIMIT × RLOAD. The PMOS pass transistor dissipates (VIN – VOUT) × ILIMIT until thermal shutdown is triggered and the device turns off. As the device cools down, it is turned on by the internal thermal-shutdown circuit. If the fault condition continues, the device cycles between current limit and thermal shutdown. See the section for more details.
The PMOS pass element in the TLV700xx-Q1 has a built-in body diode that conducts current when the voltage at OUT exceeds the voltage at IN. This current is not limited, so if extended reverse voltage operation is anticipated, external limiting to 5% of the rated output current is recommended.
7.3.2 Shutdown
The enable pin (EN) is active-high and is compatible with standard and low-voltage TTL-CMOS levels. When shutdown capability is not required, EN can be connected to the IN pin.
7.3.3 Dropout Voltage
The TLV700xx-Q1 uses a PMOS pass transistor to achieve low dropout. When (VIN – VOUT) is less than the dropout voltage (VDO), the PMOS pass device is in the linear region of operation and the input-to-output resistance is the rDS(on) of the PMOS pass element. VDO scales approximately with output current because the PMOS device behaves as a resistor in dropout.
As with any linear regulator, PSRR and transient response are degraded as (VIN – VOUT) approaches dropout. This effect is shown in Figure 13 in the section.
7.3.4 Undervoltage Lockout (UVLO)
The TLV700xx-Q1 uses an undervoltage lockout circuit to keep the output shut off until internal circuitry is operating properly.
7.4 Device Functional Modes
7.4.1 Operation With VIN Less than 2 V
The TLV700xx-Q1 family of devices operates with input voltages above 2 V. The typical UVLO voltage is 1.9 V, and the device operates at an input voltage above 2 V. When input voltage falls below the UVLO voltage, the device shuts down.
7.4.2 Operation With VIN Greater than 2 V
When VIN is greater than 2 V, if the input voltage is higher than the desired output voltage plus dropout voltage, the output voltage is equal to the desired value. Otherwise, output voltage is VIN minus the dropout voltage.
