TLV705 200-mA, Low IQ, Low-Noise, Low-Dropout Regulator in Ultra-Small, 0.77-mm × 0.77-mm DSBGA and PicoStar

1 Features

• Very Low Dropout:
  • 105 mV at I_OUT = 150 mA
  • 145 mV at I_OUT = 200 mA
• Accuracy: 0.5% Typical
• Low I_Q: 35 μA
• Available in Fixed-Output Voltages From
  0.7 V to 4.8 V
• V_IN Range: 2 V to 5.5 V
• High PSRR: 70 dB at 1 kHz
• Stable With Effective Capacitance of 0.1 μF
• Thermal Shutdown and Overcurrent Protection
• Available in an Ultra-Low Profile (0.15-mm Maximum Height) PicoStar Package Option

2 Applications

• Wireless Handsets
• Smart Phones
• Zigbee® Networks
• Bluetooth® Devices
• Other Li-Ion Operated Handheld Products
• WLAN and Other PC Add-On Cards

3 Description

The TLV705 series of low-dropout (LDO) linear regulators are low quiescent current devices with excellent line and load transient performance. These devices are designed for power-sensitive applications, with a precision band gap. An error amplifier provides typical accuracy of 0.5%. Low output noise, very high power-supply rejection ratio (PSRR), and low dropout voltage make this series of LDOs ideal for a wide selection of battery-operated handheld equipment. All devices have a thermal shutdown and current limit for safety.

Furthermore, the TLV705 series is stable with an effective output capacitance of only 0.1 μF. This feature enables the use of cost-effective capacitors that have higher bias voltage and temperature derating. The devices regulate to the specified accuracy with zero output load. The TLV705P series also provides an active pulldown circuit to quickly discharge output.

The TLV705 and TLV705P series are both available in 0.77-mm × 0.77-mm DSBGA and PicoStar packages with three height options that are optimal for handheld applications.

1. For all available packages, see the orderable addendum at the end of the data sheet.

Typical Application Circuit (Fixed-Voltage Versions)

4 Revision History

Changes from E Revision (May 2015) to F Revision

• Deleted "x" from TLV705 device in document title Go
• Changed package dimensions in document title from "0.8-mm × 0.8-mm" to "0.77-mm × 0.77-mm" Go
• Changed ultra-low profile maximum height from 0.2-mm to 0.15-mm in Applications section Go
• Changed package dimensions in Description section from 0.8-mm to 0.77-mm.Go
• Changed DSBGA package dimensions from "0.80 mm × 0.80 mm" to "0.77 mm × 0.77 mm" in the Device Information table Go
• Added copyright statement to the Typical Application Circuit Go
• Changed formatting of Thermal Information table note Go
• Deleted "x" from device number in Thermal Information table Go
• Added copyright statement to functional block diagrams in Functional Block Diagrams section Go
• Added copyright statement to Typical Application Circuit (Fixed-Voltage Versions) in the Typical Application section Go
• Changed formatting of document reference in Related Documentation section Go
• Changed table header title from "Sample & Buy" to "Order Now" in the Related Links table Go

Changes from D Revision (April 2015) to E Revision

• Added new package (YFM) to document Go
• Added PicoStar to title Go
• Changed last Features bullet Go
• Changed last sentence of Description section Go
• Added second row to Device Information table Go
• Added YFM pin out drawingGo
• Added YFM package to Thermal Information table Go
• Changed V_O parameter units in Electrical Characteristics table: % for first row, mV for second rowGo
• Changed first sentence of Overview section: removed new Go
• Changed fifth sentence of Internal Current Limit section to clarify description of the shutdown circuit functionality Go
• Changed Vµs to V/µs in second paragraph of Start-Up Current section Go
• Changed it to the start-up current in third paragraph of Start-Up Current section Go
• Changed INPUT to V_IN in Power Supply Recommendations section Go
• Added Related Links section Go
• Added YFM package to Package Mounting section Go

Changes from C Revision (October 2012) to D Revision

• Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section Go
• Added Features bullet for V_IN range Go
• Changed Applications list items Go
• Deleted Power Dissipation Ratings table Go
• Changed y-axis unit measurement from I_LIM to I_CL for Figure 11Go
• Changed Figure 31 and deleted layout silkscreen images; replaced with image of PCB layout drawing.Go
• Changed title for Figure 31 Go
• Changed title of Thermal Protection section Go

Changes from B Revision (December 2011) to C Revision

• Deleted last Features bulletGo

Changes from A Revision (August 2011) to B Revision

• Added last Features bulletGo
• Changed last sentence of Description sectionGo
• Added Mechanical Packages section (removed June 2013; packages are now automatically appended)Go
• Added YFP to title of pin out drawingGo
• Added YFP package to Thermal Information tableGo

5 Pin Configuration and Functions

YFF, YFP Packages

4-Pin DSBGA

Top View

YFM Package

4-Pin PicoStar

Top View

6 Specifications

6.6 Typical Characteristics

over operating temperature range (T_J = –40°C to +125°C), I_OUT = 10 mA, V_EN = 0.9 V, C_OUT = 1 μF, and V_IN = V_OUT(nom) + 0.5 V or 2 V, whichever is greater, unless otherwise noted. Typical values are at T_J = 25°C.

Figure 1. Line Regulation

Figure 3. Load Regulation ( 0 mA ≤ I_OUT ≤ 200 mA)

Figure 5. Dropout Voltage vs Output Current

Figure 7. Ground Pin Current vs Input Voltage

Figure 9. Ground Pin Current vs Temperature

Figure 11. Current Limit vs Input Voltage

Figure 13. Power-Supply Rejection Ratio vs Input Voltage

Figure 15. Integrated Noise vs Output Voltage

Figure 17. Load Transient 1

Figure 19. Small-Step Line Transient (10 mA)

Figure 21. V_IN Inrush Current

Figure 23. Line Transient (10 mA)

Figure 25. Power-Up and Power-Down

Figure 2. Line Regulation

Figure 4. Dropout Voltage vs Input Voltage

Figure 6. Output Voltage vs Temperature

Figure 8. Ground Pin Current vs Output Current

Figure 10. Shutdown Pin Current vs Input Voltage

Figure 12. Power-Supply Rejection Ratio vs Frequency

Figure 14. Output Spectral Noise Density vs Frequency

Figure 16. Load Transient 0

Figure 18. Load Transient 3

Figure 20. Small-Step Line Transient (200 mA)

Figure 22. V_IN Inrush Current

Figure 24. Line Transient (200 mA)

7 Detailed Description

7.2 Functional Block Diagrams

Figure 26. TLV705 Series

Figure 27. TLV705P Series

8 Application and Implementation

8.2 Typical Application

Figure 28. Typical Application Circuit (Fixed-Voltage Versions)

8.2.1 Design Requirements

Table 2 lists the design parameters.

Table 2. Design Parameters

PARAMETER	DESIGN REQUIREMENT
Input voltage	2.5 V to 3.3 V
Output voltage	1.8 V
Output current	100 mA

8.2.2 Detailed Design Procedure

Select the desired device based on the output voltage.

Provide an input supply with adequate headroom to account for dropout. The input supply must also provide adequate current to account for the GND pin current and load current.

8.2.2.1 Input and Output Capacitor Requirements

TI recommends using 1-μF X5R- and X7R-type ceramic capacitors because these components have minimal variation in value and equivalent series resistance (ESR) over temperature. However, the TLV705 series is designed to be stable with an effective capacitance of 0.1 μF or larger at the output. As a result, the device is stable with capacitors of other dielectrics as long as the effective capacitance under the operating bias voltage and temperature is greater than 0.1 μF. This effective capacitance refers to the capacitance that the LDO detects under operating bias voltage and temperature conditions (that is, the capacitance after taking the bias voltage and temperature derating into consideration). In addition to allowing the use of lower cost dielectrics, the effective capacitance enables using smaller footprint capacitors that have higher derating in space-constrained applications.

Using a 0.1-μF rating capacitor at the output of the LDO does not ensure stability because the effective capacitance under operating conditions is less than 0.1 μF. Maximum ESR must be less than 200 mΩ.

Although an input capacitor is not required for stability, good analog design practice is to connect a 0.1-μF to
1-μF low ESR capacitor across the V_IN and GND pins of the regulator. This capacitor counteracts reactive input sources and improves transient response, noise rejection, and ripple rejection. A higher-value capacitor can be necessary if large, fast rise-time load transients are anticipated, or if the device is not located close to the power source. If source impedance is more than 2 Ω, a 0.1-μF input capacitor may be necessary to ensure stability.

8.2.2.2 Transient Response

As with any regulator, increasing the size of the output capacitor reduces overshoot and undershoot magnitude, but increases the duration of the transient response.

8.2.3 Application Curves

Figure 29. Power-Supply Rejection Ratio vs Frequency

Figure 30. Power-Up and Power-Down