JAJSE96C
October 2017 – March 2024
TLV757P
PRODUCTION DATA
1
1
特長
2
アプリケーション
3
概要
4
Pin Configuration and Functions
5
Specifications
5.1
Absolute Maximum Ratings
5.2
ESD Ratings
5.3
Recommended Operating Conditions
5.4
Thermal Information
5.5
Electrical Characteristics
5.6
Typical Characteristics
6
Detailed Description
6.1
Overview
6.2
Functional Block Diagram
6.3
Feature Description
6.3.1
Undervoltage Lockout (UVLO)
6.3.2
Enable (EN)
6.3.3
Internal Foldback Current Limit
6.3.4
Thermal Shutdown
6.4
Device Functional Modes
6.4.1
Normal Operation
6.4.2
Dropout Operation
6.4.3
Disabled
7
Application and Implementation
7.1
Application Information
7.1.1
Input and Output Capacitor Selection
7.1.2
Dropout Voltage
7.1.3
Exiting Dropout
7.1.4
Reverse Current
7.1.5
Power Dissipation (PD)
7.1.5.1
Estimating Junction Temperature
7.2
Typical Application
7.2.1
Design Requirements
7.2.2
Detailed Design Procedure
7.2.2.1
Input Current
7.2.2.2
Thermal Dissipation
7.2.3
Application Curves
7.3
Power Supply Recommendations
7.4
Layout
7.4.1
Layout Guidelines
7.4.2
Layout Examples
8
Device and Documentation Support
8.1
Device Support
8.1.1
Device Nomenclature
8.2
ドキュメントの更新通知を受け取る方法
8.3
サポート・リソース
8.4
Trademarks
8.5
静電気放電に関する注意事項
8.6
用語集
9
Revision History
10
Mechanical, Packaging, and Orderable Information
パッケージ・オプション
デバイスごとのパッケージ図は、PDF版データシートをご参照ください。
メカニカル・データ(パッケージ|ピン)
DYD|5
DBV|5
DRV|6
サーマルパッド・メカニカル・データ
DRV|6
QFND087M
発注情報
jajse96c_oa
jajse96c_pm
7.4.2
Layout Examples
Figure 7-7
Layout Example: DBV Package
Figure 7-8
Layout Example: DRV Package
Figure 7-9
Layout Example: DYD Package