JAJSHL1J August   2018  – May 2021 TLV803E , TLV809E , TLV810E

PRODMIX  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Device Comparison
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Timing Diagrams
    8. 7.8 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Input Voltage (VDD)
      2. 8.3.2 VDD Hysteresis
      3. 8.3.3 VDD Glitch Immunity
      4. 8.3.4 Manual Reset (MR) Input for X2SON (DPW) Package Only
      5. 8.3.5 Output Logic
        1. 8.3.5.1 RESET Output, Active-Low
        2. 8.3.5.2 RESET Output, Active-High
    4. 8.4 Device Functional Modes
      1. 8.4.1 Normal Operation (VDD > VDD(min))
      2. 8.4.2 VDD Between VPOR and VDD(min)
      3. 8.4.3 Below Power-On-Reset (VDD < VPOR)
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application - Voltage Rail Monitoring
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
    3. 9.3 Typical Application - Overvoltage Monitoring
      1. 9.3.1 Design Requirements
      2. 9.3.2 Detailed Design Procedure
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Device Nomenclature
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 Receiving Notification of Documentation Updates
    4. 12.4 サポート・リソース
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6 Pin Configuration and Functions

GUID-809E5BF5-76C5-43D3-BE9D-F58F7C720773-low.gifFigure 6-1 DBZ Package
(Pin 1 = GND)
3-Pin SOT-23
Top View
GUID-CEE75FF1-C898-4927-986D-EB77D9DC1EFC-low.gifFigure 6-2 DCK Package
3-Pin SC-70
Top View
GUID-47FF5C4D-6594-439C-822D-37B82F20B4DF-low.gifFigure 6-3 DBZ Package
(Pin 1 = RESET, R pinout)
3-Pin SOT-23
Top View
Figure 6-5 DPW Package
5-Pin X2SON
See Table 6-1
Top View
GUID-1F3DB97C-3334-4EFF-9583-4F074D754694-low.gifFigure 6-4 DBZ Package
(Pin 3 = GND, V pinout)
3-Pin SOT-23
Top View
Table 6-1 Pin Functions
PIN I/O DESCRIPTION
NAME DCK, DBZ DBZ
(V PINOUT)		 DBZ
(R PINOUT)		 DPW
GND 1 3 2 4 — Ground
RESET 2 1 1 1 O Active-low output reset signal: This pin is driven low logic when VDD voltage falls below the negative voltage threshold (VIT–). RESET remains low (asserted) for the delay time period (tD) after VDD voltage rise above VIT+.
RESET 2 1 1 1 O Active-High output reset signal (TLV810E only): This pin is driven high logic when VDD voltage falls below the negative voltage threshold (VIT–). RESET remains high (asserted) for the delay time period (tD) after VDD voltage rise above VIT+.
VDD 3 2 3 5 I Input supply voltage. TLV803E, TLV809E, TLV810E monitor VDD voltage.
MR N/A N/A N/A 2 I Active-low manual reset input. Pull this pin to a logic low (VMR_L) to assert a reset signal in the output pin. After the MR pin is left floating or pulled to VMR_H the output goes to the nominal state after the reset delay time (tD) expires. MR can be left floating when not in use.
PAD N/A N/A N/A 3 — No Connection. Thermal pad helps with thermal dissipation. PAD does not need to be soldered down. PAD can be connected to GND.