JAJSHL1J August   2018  – May 2021 TLV803E , TLV809E , TLV810E

PRODMIX  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Device Comparison
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Timing Diagrams
    8. 7.8 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Input Voltage (VDD)
      2. 8.3.2 VDD Hysteresis
      3. 8.3.3 VDD Glitch Immunity
      4. 8.3.4 Manual Reset (MR) Input for X2SON (DPW) Package Only
      5. 8.3.5 Output Logic
        1. 8.3.5.1 RESET Output, Active-Low
        2. 8.3.5.2 RESET Output, Active-High
    4. 8.4 Device Functional Modes
      1. 8.4.1 Normal Operation (VDD > VDD(min))
      2. 8.4.2 VDD Between VPOR and VDD(min)
      3. 8.4.3 Below Power-On-Reset (VDD < VPOR)
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application - Voltage Rail Monitoring
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
    3. 9.3 Typical Application - Overvoltage Monitoring
      1. 9.3.1 Design Requirements
      2. 9.3.2 Detailed Design Procedure
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Device Nomenclature
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 Receiving Notification of Documentation Updates
    4. 12.4 サポート・リソース
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.5 Electrical Characteristics

over operating range (TA = –40℃ to 125℃), 1.7 V ≤ VDD ≤ 6 V, Rpull-up = 10 kΩ to 6 V, 10 pF load at RESET pin, unless otherwise noted. Typical values are at 25℃, VDD = 3.3V and VIT– = 2.93 V. 

 
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
COMMON PARAMETERS
VDD Input supply voltage 1.7 6 V
VIT– Input threshold voltage accuracy TA= –40℃ to 125℃ –2 0.5 2 %
VHYS Hysteresis voltage Hysteresis from VIT– 0.9 1.2 1.5 %
IDD Supply current into VDD pin VDD = 3.3 V; VDD > VIT+ (1) 0.25 1 µA
VDD = 6 V 0.4 1.2 µA
R MR Manual reset pin internal pull-up resistance X2SON (DPW) package only 100 kΩ
V MR_L Manual reset pin logic low input 0.4 V
V MR_H Manual reset pin logic high input 0.8VDD V
TLV809E (Push-Pull Active-Low)
VPOR Power on reset voltage (2) VOL ≤ 300 mV, IOUT(Sink) = 15 µA 700 mV
VOL Low level output voltage
 		 VDD = 1.7 V, VDD < VIT–, IOUT(Sink) = 500 µA 300 mV
VDD = 3.3 V, VDD < VIT–, IOUT(Sink) = 2 mA 300 mV
VOH High level output voltage
 		 VDD = 6 V, VDD > VIT+, IOUT(Source) = 4 mA 0.8VDD V
VDD = 3.3 V, VDD > VIT+, IOUT(Source) = 2 mA 0.8VDD V
TLV803E (Open-Drain Active-Low)
VPOR Power on reset voltage (2) VOL ≤ 300 mV, IOUT(Sink) = 15 µA 700 mV
VOL Low level output voltage
 		 VDD = 1.7 V, VDD < VIT–, IOUT(Sink) = 500 µA 300 mV
VDD = 3.3 V, VDD < VIT–, IOUT(Sink) = 2 mA 300 mV
Ilkg(OD) Open drain output leakage current VDD = VPULLUP = 6 V, VDD > VIT+ 100 350 nA
TLV810E (Push-Pull Active-High)
VOH High level output voltage
 		 VDD = 3.3 V, VDD < VIT–, IOUT(Source) = 2 mA 0.8VDD V
VDD = 1.7 V, VDD < VIT–, IOUT(Source) = 500 µA 0.8VDD V
VPOR Power on Reset Voltage VOH ≥ 720 mV, IOUT(Source) = 15 µA 900 mV
VOL Low level output voltage
 		 VDD = 6 V, VDD > VIT+,  IOUT(Sink) = 2 mA 300 mV
VDD = 3.3 V, VDD > VIT+, IOUT(Sink) = 500 µA 300 mV
(1) VIT+ = VIT– + VHYS
(2) Minimum VDD voltage for a controlled output state. Below VPOR, the output cannot be determined.