JAJSHL1J August   2018  – May 2021 TLV803E , TLV809E , TLV810E

PRODMIX  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Device Comparison
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Timing Diagrams
    8. 7.8 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Input Voltage (VDD)
      2. 8.3.2 VDD Hysteresis
      3. 8.3.3 VDD Glitch Immunity
      4. 8.3.4 Manual Reset (MR) Input for X2SON (DPW) Package Only
      5. 8.3.5 Output Logic
        1. 8.3.5.1 RESET Output, Active-Low
        2. 8.3.5.2 RESET Output, Active-High
    4. 8.4 Device Functional Modes
      1. 8.4.1 Normal Operation (VDD > VDD(min))
      2. 8.4.2 VDD Between VPOR and VDD(min)
      3. 8.4.3 Below Power-On-Reset (VDD < VPOR)
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application - Voltage Rail Monitoring
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
    3. 9.3 Typical Application - Overvoltage Monitoring
      1. 9.3.1 Design Requirements
      2. 9.3.2 Detailed Design Procedure
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Device Nomenclature
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 Receiving Notification of Documentation Updates
    4. 12.4 サポート・リソース
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.6 Timing Requirements

over operating range (TA = –40℃ to 125℃), 1.7 V ≤ VDD ≤ 6 V, Rpull-up = 10 kΩ to 6 V (Open Drain only), 10 pF load at RESET pin, Overdrive = 10%, unless otherwise noted. Typical values are at 25℃, VDD = 3.3 V and VIT– = 2.93 V.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
tGI Glitch immunity 5 % Overdrive(1) 10 µs
tPD_HL Propagation delay from VDD falling below VIT– to RESET VDD = (VIT+ + 30%) to (VIT– – 10%) 30 50 µs
tD Release time or reset timeout period Reset time delay variant A (2)
 		 130 200 270 ms
Reset time delay variant B (2); RUP = 100 kΩ, CL = 100 pF, 30% Overdrive (3)
 		 45 90 µs
Reset time delay variant B (2) 40 80 µs
Reset time delay variant C (2)
 		 6.5 10 13.5 ms
Reset time delay variant D (2)
 		 33 50 67 ms
Reset time delay variant F (2)
 		 260 400 540 ms
t MR_PW (4) MR pin pulse duration to initiate RESET, RESET 500 ns
t MR_RES (4) Propagation delay from MR low to RESET, RESET VDD = 4.5 V, VMR :  V MR_H to V MR_L 700 ns
t MR_tD (4) Delay from release MR to deasert RESET, RESET VDD = 4.5 V, VMR :  V MR_L to V MR_H tD_MIN tD_TYP tD_MAX ms
(1) Overdrive = [(VDD/ VIT–) - 1] × 100%. Refer to section on VDD glitch immunity
(2) Refer to Device nomenclature table. VDD: (VIT--10%) to (VIT+ + 10%)
(3) Specified by design
(4) X2SON Package only