JAJSIO2G March   2020  – March 2022 TLV9041 , TLV9042 , TLV9044

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information for Single Channel
    5. 7.5 Thermal Information for Dual Channel
    6. 7.6 Thermal Information for Quad Channel
    7. 7.7 Electrical Characteristics
    8. 7.8 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Operating Voltage
      2. 8.3.2  Rail-to-Rail Input
      3. 8.3.3  Rail-to-Rail Output
      4. 8.3.4  Common-Mode Rejection Ratio (CMRR)
      5. 8.3.5  Capacitive Load and Stability
      6. 8.3.6  Overload Recovery
      7. 8.3.7  EMI Rejection
      8. 8.3.8  Electrical Overstress
      9. 8.3.9  Input and ESD Protection
      10. 8.3.10 Shutdown Function
      11. 8.3.11 Packages With an Exposed Thermal Pad
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 TLV904x Low-Side, Current Sensing Application
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Curve
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 サポート・リソース
    4.     Trademarks
    5. 12.4 Electrostatic Discharge Caution
    6. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6 Pin Configuration and Functions

Figure 6-1 TLV9041 DBV Package
5-Pin SOT-23
Top View
Figure 6-3 TLV9041 DCK Package
5-Pin SC70
Top View
Figure 6-2 TLV9041U DBV Package
5-Pin SOT-23
Top View
Figure 6-4 TLV9041 DPW Package
5-Pin X2SON
Top View
Table 6-1 Pin Functions: TLV9041 and TLV9041U
PIN I/O DESCRIPTION
NAME NO.
TLV9041 TLV9041U
SOT-23 SC70 X2SON SOT-23
IN– 4 3 2 3 I Inverting input
IN+ 3 1 4 1 I Noninverting input
OUT 1 4 1 4 O Output
V– 2 2 3 2 I or — Negative (low) supply or ground (for single-supply operation)
V+ 5 5 5 5 I Positive (high) supply
Figure 6-5 TLV9041S DBV Package
6-Pin SOT-23
Top View
Table 6-2 Pin Functions: TLV9041S
PIN I/O DESCRIPTION
NAME NO.
IN– 4 I Inverting input
IN+ 3 I Noninverting input
OUT 1 O Output
SHDN 5 I Shutdown (low), enabled (high)
V– 2 I or — Negative (low) supply or ground (for single-supply operation)
V+ 6 I Positive (high) supply
Figure 6-6 TLV9042 D, DDF, DGK, and PW Package
8-Pin SOIC, SOT-23 8, VSSOP, and TSSOP
Top View
Connect exposed thermal pad to V–. See Section 8.3.11 for more information.
Figure 6-7 TLV9042 DSG Package
8-Pin WSON With Exposed Thermal Pad
Top View
Table 6-3 Pin Functions: TLV9042
PIN I/O DESCRIPTION
NAME NO.
IN1– 2 I Inverting input, channel 1
IN1+ 3 I Noninverting input, channel 1
IN2– 6 I Inverting input, channel 2
IN2+ 5 I Noninverting input, channel 2
OUT1 1 O Output, channel 1
OUT2 7 O Output, channel 2
V– 4 I Negative (low) supply or ground (for single-supply operation)
V+ 8 I Positive (high) supply
Figure 6-8 TLV9042S RUG Package
10-Pin X2QFN
Top View
Table 6-4 Pin Functions: TLV9042S
PIN I/O DESCRIPTION
NAME NO.
IN1– 9 I Inverting input, channel 1
IN1+ 10 I Noninverting input, channel 1
IN2– 5 I Inverting input, channel 2
IN2+ 4 I Noninverting input, channel 2
OUT1 8 O Output, channel 1
OUT2 6 O Output, channel 2
SHDN1 2 I Shutdown – low = disabled, high = enabled, channel 1
SHDN2 3 I Shutdown – low = disabled, high = enabled, channel 2
V– 1 I Negative (low) supply or ground (for single-supply operation)
V+ 7 I Positive (high) supply
Figure 6-9 TLV9044 D, PW and DYY Packages
14-Pin SOIC, TSSOP and SOT-23
Top View
Table 6-5 Pin Functions: TLV9044
PIN I/O DESCRIPTION
NAME NO.
IN1– 2 I Inverting input, channel 1
IN1+ 3 I Noninverting input, channel 1
IN2– 6 I Inverting input, channel 2
IN2+ 5 I Noninverting input, channel 2
IN3– 9 I Inverting input, channel 3
IN3+ 10 I Noninverting input, channel 3
IN4– 13 I Inverting input, channel 4
IN4+ 12 I Noninverting input, channel 4
NC — — No internal connection
OUT1 1 O Output, channel 1
OUT2 7 O Output, channel 2
OUT3 8 O Output, channel 3
OUT4 14 O Output, channel 4
V– 11 I or — Negative (low) supply or ground (for single-supply operation)
V+ 4 I Positive (high) supply