JAJSUS9A June   2024  – August 2024 TLV9044-Q1

PRODMIX  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information for Quad Channel
    5. 5.5 Electrical Characteristics
    6. 5.6 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Operating Voltage
      2. 6.3.2 Rail-to-Rail Input
      3. 6.3.3 Rail-to-Rail Output
      4. 6.3.4 Common-Mode Rejection Ratio (CMRR)
      5. 6.3.5 Capacitive Load and Stability
      6. 6.3.6 Overload Recovery
      7. 6.3.7 EMI Rejection
      8. 6.3.8 Electrical Overstress
      9. 6.3.9 Input and ESD Protection
    4. 6.4 Device Functional Modes
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 TLV904x-Q1 Low-Side, Current Sensing Application
        1. 7.2.1.1 Design Requirements
        2. 7.2.1.2 Detailed Design Procedure
        3. 7.2.1.3 Application Curve
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Documentation Support
      1. 8.1.1 Related Documentation
    2. 8.2 ドキュメントの更新通知を受け取る方法
    3. 8.3 サポート・リソース
    4.     Trademarks
    5. 8.4 静電気放電に関する注意事項
    6. 8.5 用語集
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

5.5 Electrical Characteristics

For VS = (V+) – (V–) = 1.2V to 5.5V (±0.6V to ±2.75V) at TA = 25°C, RL = 100kΩ connected to VS / 2, VCM = VS / 2, and VOUT = VS / 2, unless otherwise noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
OFFSET VOLTAGE
VOS Input offset voltage ±0.6 ±2.25 mV
TA = –40°C to 125°C ±2.5
dVOS/dT Input offset voltage drift TA = –40°C to 125°C ±0.8 µV/℃
PSRR Input offset voltage versus power supply VS = ±0.6V to ±2.75V , VCM = V– ±20 ±100 µV/V
Channel separation f = 10kHz ±5.6 µV/V
INPUT BIAS CURRENT
IB Input bias current (1) ±1 ±12 pA
IOS Input offset current (1) ±0.5 ±10 pA
NOISE
EN Input voltage noise f  = 0.1Hz to 10Hz   6.5 μVPP
eN Input voltage noise density f = 100Hz 85 nV/√Hz
f = 1kHz   66  
f = 10kHz   64  
iN Input current noise (2) f = 1kHz   20   fA/√Hz
INPUT VOLTAGE RANGE
VCM Common-mode voltage range (V–) (V+) V
CMRR Common-mode rejection ratio (V–) < VCM < (V+) – 0.7V, VS = 1.2V TA = –40°C to 125°C 60 77 dB
(V–) < VCM < (V+) – 0.7V, VS = 5.5V  75 89
(V–) < VCM < (V+), VS = 1.2V  60
(V–) < VCM < (V+), VS = 5.5V  57 72
INPUT IMPEDANCE
ZID Differential 80 || 1.4 GΩ || pF
ZICM Common-mode 100 || 0.5 GΩ || pF
OPEN-LOOP GAIN
AOL Open-loop voltage gain VS = 1.2V, (V–) + 0.2V < VO < (V+) – 0.2V,
RL = 10kΩ to VS / 2		 TA = –40°C to 125°C 98 dB
VS = 5.5V, (V–) + 0.2V < VO < (V+) – 0.2V,
RL = 10kΩ to VS / 2		 125
VS = 1.2V, (V–) + 0.1V < VO < (V+) – 0.1V,
RL = 100kΩ to VS / 2		 105
VS = 5.5V, (V–) + 0.1V < VO < (V+) – 0.1V,
RL = 100kΩ to VS / 2		 107 130
FREQUENCY RESPONSE
THD+N Total harmonic distortion + noise (3) VS = 5.5V, VCM = 2.75V, VO = 1VRMS, G = +1, f = 1kHz,
RL = 100kΩ to VS / 2		 0.013 %
GBW Gain-bandwidth product RL = 1MΩ connected to VS/2 350 kHz
SR Slew rate VS = 5.5V, G = +1, CL = 10pF 0.2 V/μs
tS Settling time To 0.1%, VS = 5.5V, VSTEP = 4V, G = +1, CL = 10pF 25 μs
To 0.1%, VS = 5.5V, VSTEP = 2V, G = +1, CL = 10pF 22
To 0.01%, VS = 5.5V, VSTEP = 4V, G = +1, CL = 10pF 35
To 0.01%, VS = 5.5V, VSTEP = 2V, G = +1, CL = 10pF 30
Phase margin G = +1, RL = 100kΩ connected to VS/2, CL = 10pF 65 °
Overload recovery time VIN  × gain > VS 13 μs
EMIRR Electro-magnetic interference rejection ratio f = 1GHz, VIN_EMIRR = 100mV 70 dB
OUTPUT
  Voltage output swing from rail Positive rail headroom VS = 1.2V,
RL = 100kΩ to VS / 2		   0.75 7 mV
VS = 5.5V,
RL = 10kΩ to VS / 2		   10 21
VS = 5.5V,
RL = 100kΩ to VS / 2		   1 8
Negative rail headroom VS = 1.2V,
RL = 100kΩ to VS / 2		   0.75 5
VS = 5.5V,
RL = 10kΩ to VS / 2		   10 21
VS = 5.5V,
RL = 100kΩ to VS / 2		   1 8
ISC Short-circuit current (4) VS = 5.5V ±40 mA
ZO Open-loop output impedance f = 10kHz 7500 Ω
POWER SUPPLY
IQ Quiescent current per amplifier VS = 5.5V, IO = 0A 10 13 µA
TA = –40°C to 125°C 13.5
SHUTDOWN
(1) Maximum IB and IOS limits are specified based on characterization results. Input differential voltages greater than 2.5V can cause increased IB
(2) Typical input current noise data is specified based on design simulation results
(3) Third-order filter; bandwidth = 80kHz at –3dB.
(4) Short-circuit current is average of sourcing and sinking short circuit currents