JAJSIO2G March   2020  – March 2022 TLV9041 , TLV9042 , TLV9044

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information for Single Channel
    5. 7.5 Thermal Information for Dual Channel
    6. 7.6 Thermal Information for Quad Channel
    7. 7.7 Electrical Characteristics
    8. 7.8 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Operating Voltage
      2. 8.3.2  Rail-to-Rail Input
      3. 8.3.3  Rail-to-Rail Output
      4. 8.3.4  Common-Mode Rejection Ratio (CMRR)
      5. 8.3.5  Capacitive Load and Stability
      6. 8.3.6  Overload Recovery
      7. 8.3.7  EMI Rejection
      8. 8.3.8  Electrical Overstress
      9. 8.3.9  Input and ESD Protection
      10. 8.3.10 Shutdown Function
      11. 8.3.11 Packages With an Exposed Thermal Pad
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 TLV904x Low-Side, Current Sensing Application
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Curve
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 サポート・リソース
    4.     Trademarks
    5. 12.4 Electrostatic Discharge Caution
    6. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

8.3.10 Shutdown Function

The TLV904xS devices feature SHDN pins that disable the op amp, placing it into a low-power standby mode. In this mode, the op amp typically consumes less than 150 nA. The SHDN pins are active low, meaning that shutdown mode is enabled when the input to the SHDN pin is a valid logic low.

The SHDN pins are referenced to the negative supply voltage of the op amp. The threshold of the shutdown feature lies around 500 mV (typical) and does not change with respect to the supply voltage. Hysteresis has been included in the switching threshold to ensure smooth switching characteristics. To ensure optimal shutdown behavior, the SHDN pins should be driven with valid logic signals. A valid logic low is defined as a voltage between V– and V– + 0.2 V. A valid logic high is defined as a voltage between V– + 1 V and V+. To enable the amplifier, the SHDN pins must be driven to a valid logic high. To disable the amplifier, the SHDN pins must be driven to a valid logic low. We highly recommend that the shutdown pin be connected to a valid high or a low voltage or driven. The maximum voltage allowed at the SHDN pins is (V+) + 0.5 V. Exceeding this voltage level will damage the device.

The SHDN pins are high-impedance CMOS inputs. Dual op amp versions are independently controlled and quad op amp versions are controlled in pairs with logic inputs. For battery-operated applications, this feature may be used to greatly reduce the average current and extend battery life. The enable time is 160 µs for full shutdown of all channels; disable time is 10 µs. When disabled, the output assumes a high-impedance state. This architecture allows the TLV904xS to be operated as a gated amplifier (or to have the device output multiplexed onto a common analog output bus). Shutdown time (tOFF) depends on loading conditions and increases as load resistance increases. To ensure shutdown (disable) within a specific shutdown time, the specified 100-kΩ load to midsupply (VS / 2) is required. If using the TLV904xS without a load, the resulting turnoff time is significantly increased.