JAJSIO2G
March 2020 – March 2022
TLV9041
,
TLV9042
,
TLV9044
PRODUCTION DATA
1
特長
2
アプリケーション
3
概要
4
Revision History
5
Device Comparison Table
6
Pin Configuration and Functions
7
Specifications
7.1
Absolute Maximum Ratings
7.2
ESD Ratings
7.3
Recommended Operating Conditions
7.4
Thermal Information for Single Channel
7.5
Thermal Information for Dual Channel
7.6
Thermal Information for Quad Channel
7.7
Electrical Characteristics
7.8
Typical Characteristics
8
Detailed Description
8.1
Overview
8.2
Functional Block Diagram
8.3
Feature Description
8.3.1
Operating Voltage
8.3.2
Rail-to-Rail Input
8.3.3
Rail-to-Rail Output
8.3.4
Common-Mode Rejection Ratio (CMRR)
8.3.5
Capacitive Load and Stability
8.3.6
Overload Recovery
8.3.7
EMI Rejection
8.3.8
Electrical Overstress
8.3.9
Input and ESD Protection
8.3.10
Shutdown Function
8.3.11
Packages With an Exposed Thermal Pad
8.4
Device Functional Modes
9
Application and Implementation
9.1
Application Information
9.2
Typical Application
9.2.1
TLV904x Low-Side, Current Sensing Application
9.2.1.1
Design Requirements
9.2.1.2
Detailed Design Procedure
9.2.1.3
Application Curve
10
Power Supply Recommendations
11
Layout
11.1
Layout Guidelines
11.2
Layout Example
12
Device and Documentation Support
12.1
Documentation Support
12.1.1
Related Documentation
12.2
Receiving Notification of Documentation Updates
12.3
サポート・リソース
Trademarks
12.4
Electrostatic Discharge Caution
12.5
Glossary
13
Mechanical, Packaging, and Orderable Information
パッケージ・オプション
メカニカル・データ(パッケージ|ピン)
DYY|14
MPSS114C
PW|14
MPDS360A
D|14
MPDS177H
サーマルパッド・メカニカル・データ
発注情報
jajsio2g_oa
jajsio2g_pm
11.2
Layout Example
Figure 11-1
Schematic Representation
Figure 11-2
Layout Example
Figure 11-3
Example Layout for VSSOP-8 (DGK) Package
Figure 11-4
Example Layout for WSON-8 (DSG) Package