JAJSIO2G March   2020  – March 2022 TLV9041 , TLV9042 , TLV9044

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information for Single Channel
    5. 7.5 Thermal Information for Dual Channel
    6. 7.6 Thermal Information for Quad Channel
    7. 7.7 Electrical Characteristics
    8. 7.8 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Operating Voltage
      2. 8.3.2  Rail-to-Rail Input
      3. 8.3.3  Rail-to-Rail Output
      4. 8.3.4  Common-Mode Rejection Ratio (CMRR)
      5. 8.3.5  Capacitive Load and Stability
      6. 8.3.6  Overload Recovery
      7. 8.3.7  EMI Rejection
      8. 8.3.8  Electrical Overstress
      9. 8.3.9  Input and ESD Protection
      10. 8.3.10 Shutdown Function
      11. 8.3.11 Packages With an Exposed Thermal Pad
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 TLV904x Low-Side, Current Sensing Application
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Curve
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 サポート・リソース
    4.     Trademarks
    5. 12.4 Electrostatic Discharge Caution
    6. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.6 Thermal Information for Quad Channel

THERMAL METRIC (1) TLV9044, TLV9044S UNIT
D
(SOIC)		 PW
(TSSOP)		 DYY
(SOT-23-14)
14 PINS 14 PINS 14 PINS
RθJA Junction-to-ambient thermal resistance 116.4 135.7 152.5 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 72.5 78.8 86.2 °C/W
RθJB Junction-to-board thermal resistance 72.4 63.9 67.4 °C/W
ψJT Junction-to-top characterization parameter 30.8 14.2 10.1 °C/W
ψJB Junction-to-board characterization parameter 72 78.3 67.2 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance n/a n/a n/a °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.