JAJSTB3B February   2024  – May 2024 TLV9051-Q1 , TLV9052-Q1

PRODMIX  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information for Single Channel
    5. 5.5 Thermal Information for Dual Channel
    6. 5.6 Thermal Information for Quad Channel
    7. 5.7 Electrical Characteristics: VS (Total Supply Voltage) = (V+) – (V–) = 1.8V to 5.5V
    8. 5.8 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Operating Voltage
      2. 6.3.2 Rail-to-Rail Input
      3. 6.3.3 Rail-to-Rail Output
      4. 6.3.4 EMI Rejection
      5. 6.3.5 Overload Recovery
      6. 6.3.6 Electrical Overstress
      7. 6.3.7 Input Protection
    4. 6.4 Device Functional Modes
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Low-Side Current Sense Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
      3. 7.2.3 Application Curve
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 Development Support
        1. 8.1.1.1 TINA-TI (Free Software Download)
    2. 8.2 Documentation Support
      1. 8.2.1 Related Documentation
    3. 8.3 ドキュメントの更新通知を受け取る方法
    4. 8.4 サポート・リソース
    5. 8.5 Trademarks
    6. 8.6 静電気放電に関する注意事項
    7. 8.7 用語集
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • DBV|5
サーマルパッド・メカニカル・データ
発注情報

5.5 Thermal Information for Dual Channel

THERMAL METRIC(1) TLV9052-Q1 UNIT
D
(SOIC)		 DGK
(VSSOP)		 PW
(TSSOP)
8 PINS 8 PINS 8 PINS
RθJA Junction-to-ambient thermal resistance TBD TBD 180.5 ℃/W
RθJC(top) Junction-to-case (top) thermal resistance TBD TBD 85.2 ℃/W
RθJB Junction-to-board thermal resistance TBD TBD 120.7 ℃/W
ψJT Junction-to-top characterization parameter TBD TBD 15.7 ℃/W
ψJB Junction-to-board characterization parameter TBD TBD 118.1 ℃/W
RθJC(bot) Junction-to-case (bottom) thermal resistance N/A N/A N/A ℃/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application note.