JAJSFE9J August   2018  – February 2024 TLV9051 , TLV9052 , TLV9054

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information for Single Channel
    5. 6.5 Thermal Information for Dual Channel
    6. 6.6 Thermal Information for Quad Channel
    7. 6.7 Electrical Characteristics: VS (Total Supply Voltage) = (V+) – (V–) = 1.8 V to 5.5 V
    8. 6.8 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Operating Voltage
      2. 7.3.2 Rail-to-Rail Input
      3. 7.3.3 Rail-to-Rail Output
      4. 7.3.4 EMI Rejection
      5. 7.3.5 Overload Recovery
      6. 7.3.6 Packages With an Exposed Thermal Pad
      7. 7.3.7 Electrical Overstress
      8. 7.3.8 Input Protection
      9. 7.3.9 Shutdown Function
    4. 7.4 Device Functional Modes
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Low-Side Current Sense Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curve
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 サポート・リソース
    4. 9.4 Trademarks
    5. 9.5 静電気放電に関する注意事項
    6. 9.6 用語集
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

5 Pin Configuration and Functions

GUID-58A2EDD2-DB57-472A-A3B5-84AE7B42315A-low.svgFigure 5-1 TLV9051 DBV, DRL Packages5-Pin SOT-23, SOT-553Top View
GUID-06B4E520-FF08-4AC2-8455-4DD8B1BE3851-low.svgFigure 5-3 TLV9051 DPW Package 5-Pin X2SONTop View
GUID-C1B96E2B-930C-41B9-9086-3EA7BD6951F2-low.svgFigure 5-2 TLV9051 DCK Package 5-Pin SC70Top View
Table 5-1 Pin Functions: TLV9051
PIN I/O DESCRIPTION
NAME SOT-23,
SOT-553		 SC-70 X2SON
IN– 4 3 2 I Inverting input
IN+ 3 1 4 I Noninverting input
OUT 1 4 1 O Output
V– 2 2 3 — Negative (low) supply or ground (for single-supply operation)
V+ 5 5 5 — Positive (high) supply
GUID-9942BCCE-3DE9-4210-9C7E-097D737EA214-low.svg Figure 5-4 TLV9051S DBV Package 6-Pin SOT-23Top View
Table 5-2 Pin Functions: TLV9051S
PIN I/O DESCRIPTION
NAME NO.
–IN 4 I Inverting input
+IN 3 I Noninverting input
OUT 1 O Output
SHDN 5 I Shutdown: low = amp disabled, high = amp enabled. See Section 7.3.9 for more information.
V– 2 — Negative (lowest) supply or ground (for single-supply operation).
V+ 6 — Positive (highest) supply
GUID-8E9A7C42-C6DA-4C20-BA20-2C6217D23BF8-low.svgFigure 5-5 TLV9052 D, DGK, PW, DDF Packages8-Pin SOIC, VSSOP, TSSOP, SOT-23Top View
GUID-F6592023-B378-49A0-B2D0-5B8B0CEA2F49-low.svg
Connect exposed thermal pad to V–. See Section 7.3.6 for more information.
Figure 5-6 TLV9052 DSG Package8-Pin WSON With Exposed Thermal PadTop View
Table 5-3 Pin Functions: TLV9052
PIN I/O DESCRIPTION
NAME NO.
IN1– 2 I Inverting input, channel 1
IN1+ 3 I Noninverting input, channel 1
IN2– 6 I Inverting input, channel 2
IN2+ 5 I Noninverting input, channel 2
OUT1 1 O Output, channel 1
OUT2 7 O Output, channel 2
V– 4 — Negative (low) supply or ground (for single-supply operation)
V+ 8 — Positive (high) supply
GUID-0F3B7677-912B-4327-9231-1014F52ED81E-low.svgFigure 5-7 TLV9052S DGS Package 10-Pin VSSOPTop View
GUID-2C1E1E20-92E3-4C62-BC61-BFC1BAD4BC9E-low.svgFigure 5-8 TLV9052S RUG Package 10-Pin X2QFNTop View
Table 5-4 Pin Functions: TLV9052S
PIN I/O DESCRIPTION
NAME VSSOP X2QFN
IN1– 2 9 I Inverting input, channel 1
IN1+ 3 10 I Noninverting input, channel 1
IN2– 8 5 I Inverting input, channel 2
IN2+ 7 4 I Noninverting input, channel 2
OUT1 1 8 O Output, channel 1
OUT2 9 6 O Output, channel 2
SHDN1 5 2 I Shutdown: low = amp disabled, high = amp enabled, channel 1. See Section 7.3.9 for more information.
SHDN2 6 3 I Shutdown: low = amp disabled, high = amp enabled, channel 2. See Section 7.3.9 for more information.
V– 4 1 — Negative (low) supply or ground (for single-supply operation)
V+ 10 7 — Positive (high) supply
GUID-6FC18D1C-B288-4D42-80AD-7BB063DAE938-low.svgFigure 5-9 TLV9054 D, PW Packages14-Pin SOIC, TSSOPTop View
GUID-3AC63543-385A-42E3-8EB6-C6AD514AF113-low.svg
Connect exposed thermal pad to V–. See Section 7.3.6 for more information.
Figure 5-11 TLV9054 RTE Package16-Pin WQFN With Exposed Thermal PadTop View
GUID-7DF2DD1B-AC70-4314-9E4E-B7B0459F3A7E-low.svgFigure 5-10 TLV9054 RUC Package14-Pin X2QFNTop View
Table 5-5 Pin Functions: TLV9054
PIN I/O DESCRIPTION
NAME SOIC, TSSOP WQFN X2QFN
IN1– 2 16 1 I Inverting input, channel 1
IN1+ 3 1 2 I Noninverting input, channel 1
IN2– 6 4 5 I Inverting input, channel 2
IN2+ 5 3 4 I Noninverting input, channel 2
IN3– 9 9 8 I Inverting input, channel 3
IN3+ 10 10 9 I Noninverting input, channel 3
IN4– 13 13 12 I Inverting input, channel 4
IN4+ 12 12 11 I Noninverting input, channel 4
NC — 6, 7 — — No internal connection
OUT1 1 15 14 O Output, channel 1
OUT2 7 5 6 O Output, channel 2
OUT3 8 8 7 O Output, channel 3
OUT4 14 14 13 O Output, channel 4
V– 11 11 10 — Negative (low) supply or ground (for single-supply operation)
V+ 4 2 3 — Positive (high) supply
GUID-9F1C8C8F-C3B4-4007-949D-99C889E08AA1-low.svg
Connect exposed thermal pad to V–. See Section 7.3.6 for more information.
Figure 5-12 TLV9054S RTE Package16-Pin WQFN With Exposed Thermal PadTop View
Table 5-6 Pin Functions: TLV9054S
PIN I/O DESCRIPTION
NAME NO.
IN1+ 1 I Noninverting input, channel 1
IN1– 16 I Inverting input, channel 1
IN2+ 3 I Noninverting input, channel 2
IN2– 4 I Inverting input, channel 2
IN3+ 10 I Noninverting input, channel 3
IN3– 9 I Inverting input, channel 3
IN4+ 12 I Noninverting input, channel 4
IN4– 13 I Inverting input, channel 4
SHDN12 6 I Shutdown: low = amp disabled, high = amp enabled, channel 1 and 2. See Section 7.3.9 for more information.
SHDN34 7 I Shutdown: low = amp disabled, high = amp enabled, channel 3 and 4. See Section 7.3.9 for more information.
OUT1 15 O Output, channel 1
OUT2 5 O Output, channel 2
OUT3 8 O Output, channel 3
OUT4 14 O Output, channel 4
V– 11 — Negative (low) supply or ground (for single-supply operation)
V+ 2 — Positive (high) supply