JAJSFE9 データシート

JAJSFE9J August 2018 – February 2024 TLV9051 , TLV9052 , TLV9054

PRODUCTION DATA

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）

DPW|5
- MPSS088
DCK|5
- MPDS025J
DBV|5
- MPDS018T
DBV|6
- MPDS026Q

サーマルパッド・メカニカル・データ

DPW|5
- QFND567C

発注情報

6.8 Typical Characteristics

at T_A = 25°C, V_S = 5.5V, R_L = 10kΩ connected to V_S / 2, V_CM = V_S / 2, and V_OUT = V_S / 2 (unless otherwise noted)

V_S = 5.5V

Figure 6-1 Offset Voltage Production Distribution

Figure 6-3 Offset Voltage vs Temperature

Figure 6-5 Offset Voltage vs Power Supply

Figure 6-7 Input Bias Current and Offset Current vs Common-Mode Voltage

Figure 6-9 Input Voltage Noise Spectral Density vs Frequency

Figure 6-11 CMRR vs Temperature

V_S = 5.5V, T_A = –40°C to 125°C

Figure 6-2 Offset Voltage Drift Distribution

Figure 6-4 Offset Voltage vs Common-Mode Voltage

Figure 6-6 Input Bias Current vs Temperature

Figure 6-8 0.1-Hz to 10-Hz Input Voltage Noise

Figure 6-10 CMRR and PSRR vs Frequency (Referred to Input)

V_S = 1.8V to 5.5V

Figure 6-12 PSRR vs Temperature

Figure 6-13 Open Loop Voltage Gain and Phase vs Frequency

Figure 6-15 Open Loop Voltage Gain vs Output Voltage

Figure 6-17 Phase Margin vs Capacitive Load

	G = +1V/V
V_OUT step = 100mV_p-p

Figure 6-19 Small-Signal Overshoot vs Load Capacitance

Figure 6-21 Slew Rate vs Capacitive Load

	G = +1V/V
	V_OUT step = 10mV_p-p

Figure 6-23 Small-Signal Step Response

	G = +1V/V
	V_OUT step = 4V_p-p

Figure 6-25 Large-Signal Step Response

C_L = 100pF	G = +1V/V

Figure 6-27 Positive Large-Signal Settling Time

V_OUT = 0.5V_RMS	G = +1	V_CM = 2.5V
	BW = 80kHz

Figure 6-29 THD + N vs Frequency

Figure 6-31 Output Voltage Swing vs Output Current

Figure 6-33 Short-Circuit Current vs Temperature

Figure 6-35 Quiescent Current vs Temperature

P_RF = –10dBm

Figure 6-37 Electromagnetic Interference Rejection Ratio Referred to Noninverting Input (EMIRR+) vs Frequency

Figure 6-14 Open Loop Voltage Gain vs Temperature

Figure 6-16 Closed Loop Voltage Gain vs Frequency

Figure 6-18 No Phase Reversal

	G = –1V/V
	V_OUT step = 100mV_p-p

Figure 6-20 Small-Signal Overshoot vs Load Capacitance

	G = –10V/V

Figure 6-22 Overload Recovery

	G = –1V/V
	V_OUT step = 10mV_p-p

Figure 6-24 Small-Signal Step Response

	G = –1V/V
	V_OUT step = 4V_p-p

Figure 6-26 Large-Signal Step Response

C_L = 100pF	G = +1V/V

Figure 6-28 Negative Large-Signal Settling Time

f = 1kHz	G = +1	V_CM = 2.5V
	BW = 80kHz

Figure 6-30 THD + N vs Amplitude

Figure 6-32 Maximum Output Voltage vs Frequency and Supply Voltage

Figure 6-34 Quiescent Current vs Supply Voltage

Figure 6-36 Open-Loop Output Impedance vs Frequency

P_RF = –10dBm

Figure 6-38 Channel Separation vs Frequency