JAJSFE9J
August 2018 – February 2024
TLV9051
,
TLV9052
,
TLV9054
PRODUCTION DATA
1
1
特長
2
アプリケーション
3
概要
4
Device Comparison Table
5
Pin Configuration and Functions
6
Specifications
6.1
Absolute Maximum Ratings
6.2
ESD Ratings
6.3
Recommended Operating Conditions
6.4
Thermal Information for Single Channel
6.5
Thermal Information for Dual Channel
6.6
Thermal Information for Quad Channel
6.7
Electrical Characteristics: VS (Total Supply Voltage) = (V+) – (V–) = 1.8 V to 5.5 V
6.8
Typical Characteristics
7
Detailed Description
7.1
Overview
7.2
Functional Block Diagram
7.3
Feature Description
7.3.1
Operating Voltage
7.3.2
Rail-to-Rail Input
7.3.3
Rail-to-Rail Output
7.3.4
EMI Rejection
7.3.5
Overload Recovery
7.3.6
Packages With an Exposed Thermal Pad
7.3.7
Electrical Overstress
7.3.8
Input Protection
7.3.9
Shutdown Function
7.4
Device Functional Modes
8
Application and Implementation
8.1
Application Information
8.2
Typical Low-Side Current Sense Application
8.2.1
Design Requirements
8.2.2
Detailed Design Procedure
8.2.3
Application Curve
8.3
Power Supply Recommendations
8.4
Layout
8.4.1
Layout Guidelines
8.4.2
Layout Example
9
Device and Documentation Support
9.1
Documentation Support
9.1.1
Related Documentation
9.2
Receiving Notification of Documentation Updates
9.3
サポート・リソース
9.4
Trademarks
9.5
静電気放電に関する注意事項
9.6
用語集
10
Revision History
11
Mechanical, Packaging, and Orderable Information
パッケージ・オプション
メカニカル・データ(パッケージ|ピン)
RTE|16
MPQF149D
RUC|14
MPQF212D
PW|14
MPDS360
D|14
MPDS177G
サーマルパッド・メカニカル・データ
RTE|16
QFND525B
RUC|14
QFND283A
PW|14
QFND305D
発注情報
jajsfe9j_oa
jajsfe9j_pm
7.2
Functional Block Diagram