JAJSUS7 June   2024 TLV9304-Q1

PRODMIX  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information for Quad Channel
    5. 5.5 Electrical Characteristics
    6. 5.6 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Input Protection Circuitry
      2. 6.3.2 EMI Rejection
      3. 6.3.3 Phase Reversal Protection
      4. 6.3.4 Thermal Protection
      5. 6.3.5 Capacitive Load and Stability
      6. 6.3.6 Common-Mode Voltage Range
      7. 6.3.7 Electrical Overstress
      8. 6.3.8 Overload Recovery
      9. 6.3.9 Typical Specifications and Distributions
    4. 6.4 Device Functional Modes
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Applications
      1. 7.2.1 High Voltage Precision Comparator
        1. 7.2.1.1 Design Requirements
        2. 7.2.1.2 Detailed Design Procedure
        3. 7.2.1.3 Application Curve
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 Development Support
        1. 8.1.1.1 TINA-TI (Free Software Download)
    2. 8.2 Documentation Support
      1. 8.2.1 Related Documentation
    3. 8.3 ドキュメントの更新通知を受け取る方法
    4. 8.4 サポート・リソース
    5. 8.5 Trademarks
    6. 8.6 静電気放電に関する注意事項
    7. 8.7 用語集
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

4 Pin Configuration and Functions

Figure 4-1 TLV9301-Q1 DBV Package
5-Pin SOT-23(1)
Top View
Figure 4-2 TLV9301-Q1 DCK Package
5-Pin SC70(2)
Top View
Table 4-1 Pin Functions: TLV9301-Q1
PINI/ODESCRIPTION
NAMEDBVDCK
+IN31INoninverting input
–IN43IInverting input
OUT14OOutput
V+55—Positive (highest) power supply
V–22—Negative (lowest) power supply
(1) DBV (SOT-23) package is preview only.
(2) DCK (SC70) package is preview only.
TLV9304-Q1 TLV9302-Q1 D and PW Package8-Pin SOIC and TSSOP#GUID-2D270B79-D2F2-4F2E-9B1F-B9FBF7237616/GUID-89B365DE-7534-4536-BA63-9F117BB68E53Top View Figure 4-3 TLV9302-Q1 D and PW Package
8-Pin SOIC and TSSOP(1)
Top View
Table 4-2 Pin Functions: TLV9302-Q1
PIN I/O DESCRIPTION
NAME NO.
+IN A 3 I Noninverting input, channel A
+IN B 5 I Noninverting input, channel B
–IN A 2 I Inverting input, channel A
–IN B 6 I Inverting input, channel B
OUT A 1 O Output, channel A
OUT B 7 O Output, channel B
V+ 8 — Positive (highest) power supply
V– 4 — Negative (lowest) power supply
(1) D (SOIC) and PW (TSSOP) packages are preview only.
Figure 4-4 TLV9304-Q1 D and PW Package
14-Pin SOIC(1) and TSSOP
Top View
Table 4-3 Pin Functions: TLV9304-Q1
PINI/ODESCRIPTION
NAMENO.
+IN A3INoninverting input, channel A
+IN B5INoninverting input, channel B
+IN C10INoninverting input, channel C
+IN D12INoninverting input, channel D
–IN A2IInverting input, channel A
–IN B6IInverting input, channel B
–IN C9IInverting input, channel C
–IN D13IInverting input, channel D
OUT A1OOutput, channel A
OUT B7OOutput, channel B
OUT C8OOutput, channel C
OUT D14OOutput, channel D
V+4—Positive (highest) power supply
V–11—Negative (lowest) power supply
(1) D (SOIC) package is preview only.