JAJSL05B November   2021  – March 2022 TLV9361 , TLV9362 , TLV9364

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information for Single Channel
    5. 6.5 Thermal Information for Dual Channel
    6. 6.6 Thermal Information for Quad Channel
    7. 6.7 Electrical Characteristics
    8. 6.8 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 EMI Rejection
      2. 7.3.2 Thermal Protection
      3. 7.3.3 Capacitive Load and Stability
      4. 7.3.4 Electrical Overstress
      5. 7.3.5 Overload Recovery
      6. 7.3.6 Typical Specifications and Distributions
    4. 7.4 Device Functional Modes
  8. 8 Application Information Disclaimer
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Unity-Gain Buffer With RISO Stability Compensation
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curve
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Development Support
        1. 11.1.1.1 TINA-TI (Free Software Download)
        2. 11.1.1.2 TI Precision Designs
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 サポート・リソース
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

5 Pin Configuration and Functions

Figure 5-1 TLV9361 DBV Package
5-Pin SOT-23
(Top View)
Figure 5-2 TLV9361 DCK Package
5-Pin SC70
(Top View)
Table 5-1 Pin Functions: TLV9361
PIN I/O DESCRIPTION
NAME SOT-23 SC70
IN+ 3 1 I Noninverting input
IN– 4 3 I Inverting input
OUT 1 4 O Output
V+ 5 5 — Positive (highest) power supply
V– 2 2 — Negative (lowest) power supply
Figure 5-3 TLV9362 D, DDF, DGK, and PW Package
8-Pin SOIC, SOT-23, VSSOP, and TSSOP
(Top View)
Table 5-2 Pin Functions: TLV9362
PIN I/O DESCRIPTION
NAME NO.
IN1+ 3 I Noninverting input, channel 1
IN1– 2 I Inverting input, channel 1
IN2+ 5 I Noninverting input, channel 2
IN2– 6 I Inverting input, channel 2
OUT1 1 O Output, channel 1
OUT2 7 O Output, channel 2
V+ 8 — Positive (highest) power supply
V– 4 — Negative (lowest) power supply
Figure 5-4 TLV9364 D and PW Package
SOIC and TSSOP
(Top View)
Table 5-3 Pin Functions: TLV9364
PIN I/O DESCRIPTION
NAME NO.
IN1+ 3 I Noninverting input, channel 1
IN1– 2 I Inverting input, channel 1
IN2+ 5 I Noninverting input, channel 2
IN2– 6 I Inverting input, channel 2
IN3+ 10 I Noninverting input, channel 3
IN3– 9 I Inverting input, channel 3
IN4+ 12 I Noninverting input, channel 4
IN4– 13 I Inverting input, channel 4
OUT1 1 O Output, channel 1
OUT2 7 O Output, channel 2
OUT3 8 O Output, channel 3
OUT4 14 O Output, channel 4
V+ 4 — Positive (highest) power supply
V– 11 — Negative (lowest) power supply