| RT |
1 |
I |
Frequency setting pin. This
analog pin is used to set the switching frequency between 200 kHz
and 2.2 MHz by placing an external resistor from this pin to AGND.
Do not leave open or connect to ground. |
| EN |
2 |
I |
Precision enable input pin. High
= on, low = off. Can be connected to VIN. Precision enable allows
the pin to be used as an adjustable UVLO. Place an external voltage
divider between this pin, AGND, and VIN to create an external
UVLO. |
| VIN |
3, 4, 18, 19 |
P |
Input supply voltage. Connect the
input supply to these pins. Connect input capacitors between these
pins and PGND in close proximity to the device. Refer to Section 11.2 for input capacitor placement example. |
| PGND |
5, 6, 16, 17, 28, 29 |
G |
Power ground. This pin is the
return current path for the power stage of the device. Connect this
pad to the input supply return, the load return, and the capacitors
associated with the VIN and VOUT pins. See Section 11.2 for a recommended layout. |
| VOUT |
7-10, 12–15, 30 |
P |
Output voltage. These pins are
connected to the internal output inductor. Connect these pins to the
output load and connect external output capacitors between these
pins and PGND. |
| SW |
11 |
O |
Switch node. Do not place any
external component on this pin or connect to any signal. The amount
of copper placed on these pins must be kept to a minimum to prevent
issues with noise and EMI. |
| NC |
20, 21 |
–— |
No connect. Do not connect these
pins to ground, to another DNC pin, or to any other voltage. These
pins are connected to internal circuitry. Each pin must be soldered
to an isolated pad. |
| VLDOIN |
22 |
P |
Optional LDO supply input.
Connect to VOUT or to other voltage rail to improve efficiency.
Connect an optional high quality 0.1-μF to 1-μF capacitor from this
pin to ground for improved noise immunity. Do not connect to a
voltage above 12 V or to a voltage greater than VIN. If
unused, connect this pin to ground. |
| VCC |
23 |
O |
Internal LDO output. Used as a
supply to the internal control circuits. Do not connect to any
external loads. Connect a high-quality 1-μF ceramic capacitor from
this pin to PGND. |
| AGND |
24, 27 |
G |
Analog ground. Zero voltage
reference for internal references and logic. All electrical
parameters are measured with respect to this pin. This pin must
be connected to PGND at a single point. See Section 11.2 for a recommended layout. |
| FB |
25 |
I |
Feedback input. For the
adjustable output version, connect the mid-point of the feedback
resistor divider to this pin. Connect the upper resistor
(RFBT) of the feedback divider to VOUT at
the desired point of regulation. Connect the lower resistor
(RFBB) of the feedback divider to AGND. When
connecting with a feedback resistor divider, keep this FB trace
short and as small as possible to avoid noise coupling. See Section 11.2 for a feedback resistor placement. |
| PG |
26 |
O |
Power-good monitor. Open-drain
output that asserts low if the feedback voltage is not within the
specified window thresholds. A 10-kΩ to 100-kΩ pullup resistor is
required to a suitable pullup voltage. If not used, this pin can be
left open or connected to PGND. |
