JAJSN58 April   2022 TLVM13620

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics
    6. 7.6  System Characteristics
    7. 7.7  Typical Characteristics
    8. 7.8  Typical Characteristics — 2-A Device (VIN = 12 V)
    9. 7.9  Typical Characteristics — 2-A Device (VIN = 24 V)
    10. 7.10 Typical Characteristics — 2-A Device (VIN = 36 V)
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Input Voltage Range
      2. 8.3.2  Adjustable Output Voltage (FB)
      3. 8.3.3  Input Capacitors
      4. 8.3.4  Output Capacitors
      5. 8.3.5  Switching Frequency (RT)
      6. 8.3.6  Output ON and OFF Enable (EN) and VIN UVLO
      7. 8.3.7  Power-Good Monitor (PG)
      8. 8.3.8  Internal LDO, VCC Output, and VLDOIN Input
      9. 8.3.9  Overcurrent Protection (OCP)
      10. 8.3.10 Thermal Shutdown
    4. 8.4 Device Functional Modes
      1. 8.4.1 Shutdown Mode
      2. 8.4.2 Standby Mode
      3. 8.4.3 Active Mode
  9. 9 Applications and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Design 1 — 2-A Synchronous Buck Regulator for Industrial Applications
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 Custom Design With WEBENCH® Tools
          2. 9.2.1.2.2 Output Voltage Setpoint
          3. 9.2.1.2.3 Switching Frequency Selection
          4. 9.2.1.2.4 Input Capacitor Selection
          5. 9.2.1.2.5 Output Capacitor Selection
          6. 9.2.1.2.6 Other Connections
        3. 9.2.1.3 Application Curves
      2. 9.2.2 Design 2 — Inverting Buck-Boost Regulator with a –5-V Output
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
          1. 9.2.2.2.1 Output Voltage Setpoint
          2. 9.2.2.2.2 IBB Maximum Output Current
          3. 9.2.2.2.3 Switching Frequency Selection
          4. 9.2.2.2.4 Input Capacitor Selection
          5. 9.2.2.2.5 Output Capacitor Selection
          6. 9.2.2.2.6 Other Connections
          7. 9.2.2.2.7 EMI
            1. 9.2.2.2.7.1 EMI Plots
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
      1. 11.2.1 Package Specifications
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Third-Party Products Disclaimer
      2. 12.1.2 Development Support
        1. 12.1.2.1 Custom Design With WEBENCH® Tools
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 Receiving Notification of Documentation Updates
    4. 12.4 サポート・リソース
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.5 Electrical Characteristics

Limits apply over TJ = –40°C to 125°C, VIN = 24 V, VOUT = 3.3 V, VLDOIN = 5 V, fSW = 800 kHz (unless otherwise noted). Minimum and maximum limits are specified through production test or by design. Typical values represent the most likely parametric norm and are provided for reference only.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY VOLTAGE
VIN Input operating voltage range Needed to start up (over IOUT range) 3.95 36 V
Once operating (over IOUT range) 3 36 V
VIN_HYS Hysteresis(1) 1.0 V
IQ_VIN Input operating quiescent current (non-switching)  TA = 25°C, VEN = 3.3 V, VFB = 1.5 V 4 µA
ISDN_VIN VIN shutdown quiescent current VEN = 0 V, TA = 25°C 3 µA
ENABLE
VEN_RISE EN voltage rising threshold 1.161 1.263 1.365 V
VEN_FALL EN voltage falling threshold 0.91 V
VEN_HYS EN voltage hysteresis 0.275 0.353 0.404 V
VEN_WAKE EN wake-up threshold 0.4 V
IEN Input current into EN (non-switching) VEN = 3.3 V, VFB = 1.5 V 1.65 µA
tEN EN HIGH to start of switching delay(1) 0.7 ms
INTERNAL LDO VCC
VCC Internal LDO VCC output voltage 3.4 V ≤ VLDOIN ≤ 12.5 V 3.3 V
VLDOIN = 3.1 V, non-switching 3.1 V
VCC_UVLO VCC UVLO rising threshold VLDOIN < 3.1 V(1) 3.6 V
VIN < 3.6 V(2) 3.6 V
VCC_UVLO_HYS VCC UVLO hysteresis(2) Hysteresis below VCC_UVLO 1.1 V
IVLDOIN Input current into VLDOIN pin (non-switching, maximum at TA = 125°C)(3) VEN = 3.3 V, VFB = 1.5 V 25 31.2 µA
FEEDBACK
VOUT Adjustable output voltage range  Over the IOUT range 1 6 V
VFB Feedback voltage TA = 25°C, IOUT = 0 A 1.0 V
VFB_ACC Feedback voltage accuracy Over the VIN range, VOUT = 1 V, IOUT = 0 A, fSW = 200 kHz –1% +1%
VFB Load regulation TA = 25°C, 0 A ≤ IOUT ≤ 3 A 0.1%
VFB Line regulation TA = 25°C, IOUT = 0 A, 4.0 V ≤ VIN ≤ 36 V 0.1%
IFB Input current into the FB pin VFB = 1.0 V 10 nA
CURRENT
IOUT Output current  TA = 25°C 0 2.0 A
IOCL Output overcurrent (DC) limit threshold  3.8 A
IL_HS High-side switch current limit  Duty cycle approaches 0% 4.48 4.87 5.32 A
IL_LS Low-side switch current limit  2.07 2.4 2.80 A
IL_NEG Negative current limit  –3 A
VHICCUP Ratio of FB voltage to in-regulation FB voltage to enter hiccup Not during soft start 40%
tW Short circuit wait time ("hiccup" time before soft start)(1) 80 ms
SOFT START
tSS Time from first SW pulse to VREF at 90% VIN ≥ 4.2 V 3.5 5 7 ms
tSS2 Time from first SW pulse to release of FPWM lockout if the output not in regulation(1) VIN ≥ 4.2 V 9.5 13 17 ms
POWER GOOD
PGOV PG upper threshold — rising % of VOUT setting 105% 107% 110%
PGUV PG lower threshold — falling
% of VOUT setting

 92% 94% 96.5%
PGHYS PG upper threshold hysteresis (rising and falling)
% of VOUT setting

 1.3%
VIN_PG_VALID Input voltage for valid PG output 46-μA pullup, VEN = 0 V 1.0 V
VPG_LOW Low level PG function output voltage 2-mA pullup to the PG pin, VEN = 3.3 V 0.4 V
IPG Input current into the PG pin when open-drain output is high VPG = 3.3 V 10 nA
IOV Pulldown current at the SW node under overvoltage condition 0.5 mA
tPG_FLT_RISE Delay time to PG high signal 1.5 2.0 2.5 ms
tPG_FLT_FALL Glitch filter time constant for PG function 120 µs
SWITCHING FREQUENCY
fSW_RANGE Switching frequency range by RT or SYNC 200 2200 kHz
fSW_RT1 Default switching frequency by RT RRT = 66.5 kΩ 180 200 220 kHz
fSW_RT2 Default switching frequency by RT VIN = 12 V, RRT  = 5.76 kΩ 1980 2200 2420 kHz
SYNCHRONIZATION
tB Blanking of EN after rising or falling edges(1) 4 28 µs
tSYNC_EDGE Enable sync signal hold time after edge for edge recognition(1) 100 ns
POWER STAGE
VBOOT_UVLO Voltage on CBOOT pin compared to SW which will turn off high-side switch 2.1 V
tON_MIN Minimum ON pulse width(1) VOUT = 1 V, IOUT = 1 A 55 70 ns
tON_MAX Maximum ON pulse width(1) 9 µs
tOFF_MIN Minimum OFF pulse width VIN = 4 V, IOUT = 1 A 65 85 ns
THERMAL SHUTDOWN
TSDN Thermal shutdown threshold (1) Temperature rising 158 168 180 °C
THYST Thermal shutdown hysteresis(1) 10 °C
(1) Parameter specified by design, statistical analysis and production testing of correlated parameters. Not production tested.
(2) Production tested with VIN = 3 V.
(3) This specification is the current used by the device while not switching, open loop, with FB pulled to +5% of nominal. This specification does not represent the total input current to the system while regulating. For additional information, reference the Systems Characteristics and the Input Supply Current sections.