| VIN1, VIN2 |
1, 16 |
P |
Input supply voltage. Connect the input supply to
these pins. Connect input capacitors between these pins and PGND in
close proximity to the device. |
| SW |
2 |
O |
Switch node. Do not place any external component
on this pin or connect to any signal. The amount of copper placed on
this pin must be kept to a minimum to prevent issues with noise and
EMI. |
| CBOOT |
3 |
I/O |
Bootstrap pin for the internal high-side gate
driver. A 100-nF bootstrap capacitor is internally connected from
this pin to SW within the module to provide the bootstrap voltage.
CBOOT is brought out to use in conjunction with RBOOT to effectively
lower the value of the internal series bootstrap resistance to
adjust the switch-node slew rate, if necessary. |
| RBOOT |
4 |
I/O |
External bootstrap resistor connection. Internal
to the device, a 100-Ω bootstrap resistor is connected between RBOOT
and CBOOT. RBOOT is brought out to use in conjunction with CBOOT to
effectively lower the value of the internal series bootstrap
resistance to adjust the switch-node slew rate, if necessary.
|
| VLDOIN |
5 |
P |
Input bias voltage. Input to the internal LDO
that supplies the internal control circuits. Connect to an output
voltage point to improve efficiency. Connect an optional
high-quality 0.1-μF to 1-μF capacitor from this pin to ground for
improved noise immunity. If the output voltage is above 12 V,
connect this pin to ground. |
| AGND |
6, 11 |
G |
Analog ground. Zero-voltage reference for
internal references and logic. All electrical parameters are
measured with respect to this pin. These pins must be connected
to PGND. See Section 11.2
for a recommended layout. |
| VCC |
7 |
O |
Internal LDO output. Used as a supply to the
internal control circuits. Do not connect to any external loads. A
1-μF capacitor internally connects from VCC to AGND. |
| VOUT1, VOUT2 |
8, 9 |
P |
Output voltage. These pins are connected to the
internal buck inductor. Connect these pins to the output load and
connect external output capacitors between these pins and
PGND. |
| FB |
10 |
I |
Feedback input. Connect the midpoint of the
feedback resistor divider to this pin. Connect the upper resistor
(RFBT) of the feedback divider to VOUT at
the desired point of regulation. Connect the lower resistor
(RFBB) of the feedback divider to AGND. Do not leave
open or connect to ground. |
| RT |
12 |
I |
Frequency setting pin used to set the switching
frequency between 200 kHz and 2.2 MHz by placing an external
resistor from RT to AGND. Do not leave open or connect to
ground. |
| PG |
13 |
O |
Open-drain power-good monitor output that asserts
low if the FB voltage is not within the specified window thresholds.
A 10-kΩ to 100-kΩ pullup resistor to a suitable voltage is required.
If not used, PG can be left open or connected to GND. |
| EN |
14 |
I |
Precision enable input pin. High = on, Low = off.
Can be connected to VIN. Precision enable allows the pin to be used
as an adjustable input voltage UVLO. The module can be turned off by
using an open-drain/collector device to connect this pin to AGND.
Connect an external resistor divider between this pin, VIN and AGND
to create an external UVLO. |
| NC |
15 |
— |
No connection. Tie to GND or leave open. |
| PGND |
17, 18, 19, 20 |
G |
Power ground. This is the return current path for
the power stage of the device. Connect these pads to the input
supply return, the load return, and the capacitors associated with
the VIN and VOUT pins. See Section 11.2
for a recommended layout. |
