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  • TLVM13660 高密度、3V～36V 入力、1V～6V 出力、6A 同期整流式降圧 DC/DC パワー・モジュール、Enhanced HotRod™ QFN パッケージ

    • JAJSMY7 April   2022 TLVM13660

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  • TLVM13660 高密度、3V～36V 入力、1V～6V 出力、6A 同期整流式降圧 DC/DC パワー・モジュール、Enhanced HotRod™ QFN パッケージ
  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 System Characteristics
    7. 7.7 Typical Characteristics
    8. 7.8 Typical Characteristics (VIN = 12 V)
    9. 7.9 Typical Characteristics (VIN = 24 V)
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Input Voltage Range (VIN1, VIN2)
      2. 8.3.2  Adjustable Output Voltage (FB)
      3. 8.3.3  Input Capacitors
      4. 8.3.4  Output Capacitors
      5. 8.3.5  Switching Frequency (RT)
      6. 8.3.6  Precision Enable and Input Voltage UVLO (EN)
      7. 8.3.7  Power Good Monitor (PG)
      8. 8.3.8  Adjustable Switch-Node Slew Rate (RBOOT, CBOOT)
      9. 8.3.9  Bias Supply Regulator (VCC, VLDOIN)
      10. 8.3.10 Overcurrent Protection (OCP)
      11. 8.3.11 Thermal Shutdown
    4. 8.4 Device Functional Modes
      1. 8.4.1 Shutdown Mode
      2. 8.4.2 Standby Mode
      3. 8.4.3 Active Mode
  9. 9 Applications and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Design 1 – High-Efficiency 6-A Synchronous Buck Regulator for Industrial Applications
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 Custom Design With WEBENCH® Tools
          2. 9.2.1.2.2 Output Voltage Setpoint
          3. 9.2.1.2.3 Switching Frequency Selection
          4. 9.2.1.2.4 Input Capacitor Selection
          5. 9.2.1.2.5 Output Capacitor Selection
          6. 9.2.1.2.6 Other Connections
        3. 9.2.1.3 Application Curves
      2. 9.2.2 Design 2 – Inverting Buck-Boost Regulator with Negative Output Voltage
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
          1. 9.2.2.2.1 Output Voltage Setpoint
          2. 9.2.2.2.2 IBB Maximum Output Current
          3. 9.2.2.2.3 Switching Frequency Selection
          4. 9.2.2.2.4 Input Capacitor Selection
          5. 9.2.2.2.5 Output Capacitor Selection
          6. 9.2.2.2.6 Other Considerations
        3. 9.2.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Thermal Design and Layout
    2. 11.2 Layout Example
      1. 11.2.1 Package Specifications
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Third-Party Products Disclaimer
      2. 12.1.2 Development Support
        1. 12.1.2.1 Custom Design With WEBENCH® Tools
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 Receiving Notification of Documentation Updates
    4. 12.4 サポート・リソース
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 Glossary
  13. 13Mechanical, Packaging, and Orderable Information
  14. 重要なお知らせ

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DATA SHEET

TLVM13660 高密度、3V～36V 入力、1V～6V 出力、6A 同期整流式降圧 DC/DC パワー・モジュール、Enhanced HotRod™ QFN パッケージ

このリソースの元の言語は英語です。 翻訳は概要を便宜的に提供するもので、自動化ツール (機械翻訳) を使用していることがあり、TI では翻訳の正確性および妥当性につきましては一切保証いたしません。 実際の設計などの前には、ti.com で必ず最新の英語版をご参照くださいますようお願いいたします。

1 特長

  • 用途の広い 同期整流式降圧 DC/DC パワー・モジュール
    • MOSFET、インダクタ、コントローラを内蔵
    • 広い入力電圧範囲：3V～36V
    • 出力電圧を調整可能 1V～6V、温度範囲全体にわたってセットポイント精度 1%
    • 5.0mm × 5.5mm × 4mm のオーバーモールド・パッケージ
    • –40℃～125℃の接合部温度範囲
    • 200kHz～2.2MHz の範囲で周波数を調整可能
    • 負電圧出力に対応可能
  • 全負荷範囲にわたって極めて高い効率を実現
    • 95% 以上のピーク効率
    • 外部バイアス・オプションによる効率向上
    • シャットダウン時静止電流：0.6µA (標準値)
    • 6A 負荷でのドロップアウト電圧：0.8V (標準値)
  • 非常に小さい伝導および放射 EMI シグネチャ
    • デュアル入力パスと内蔵コンデンサを備えた低ノイズ・パッケージにより、スイッチのリンギングが減少
    • 抵抗により調整可能なスイッチ・ノードのスルーレート
    • 固定周波数 FPWM 動作モード
    • CISPR 11 および 32 Class B の放射規格に準拠
  • スケーラブルな電源に好適
    • TLVM13640 (36V、4A) とピン互換
  • 堅牢な設計のための本質的な保護機能
    • 高精度のイネーブル入力とオープン・ドレインの PGOOD インジケータによるシーケンシング、制御、VIN UVLO
    • 過電流およびサーマル・シャットダウン保護機能
  • WEBENCH® Power Designer により、TLVM13660 を使用するカスタム設計を作成

2 アプリケーション

  • 試験および測定、航空宇宙および防衛
  • ファクトリ・オートメーション / 制御
  • 降圧および反転型の昇降圧電源

3 概要

同期整流式降圧モジュール・ファミリから派生した TLVM13660 は、パワー MOSFET、シールド付きインダクタ、受動部品を Enhanced HotRod™ QFN パッケージに実装した高集積 36V、6A DC/DC ソリューションです。このモジュールは、VIN および VOUT ピンをパッケージの角に配置し、入力および出力コンデンサの配置を最適化しています。モジュールの下面には大きな 4 つのサーマル・パッドがあるため、単純なレイアウトが可能で、製造時の扱いも容易です。

出力電圧範囲が 1V～6V であるため、TLVM13660 は小さな PCB フットプリントで低 EMI の設計を迅速かつ容易に実装できるよう設計されています。このトータル・ソリューションを使用すると、外付け部品はわずか 4 個で済み、設計プロセスで磁気および補償のための部品選択も不要です。

TLVM13660 モジュールは、スペースが制約される用途での小型化と簡素化をめざして設計されているだけでなく、堅牢性の高い性能を実現するためのさまざまな機能を備えています。その例としては、可変入力電圧 UVLO 用のヒステリシス付き高精度イネーブル、抵抗を使ってプログラム可能なスイッチ・ノードのスルーレートによる EMI 改善、内蔵 VCC、ブートストラップおよび入力コンデンサによる信頼性向上と高密度化、全負荷電流範囲にわたって一定のスイッチング周波数、負電圧出力能力、シーケンシング、障害保護、出力電圧監視用の PGOOD インジケータがあります。

製品情報
部品番号 パッケージ(1) 本体サイズ (公称)
TLVM13660 B3QFN (20) 5.0mm × 5.5mm
(1) 利用可能なパッケージについては、このデータシートの末尾にある注文情報を参照してください。
代表的な回路図
代表的な効率 (VOUT = 5V、fSW = 1MHz)

4 Revision History

DATE REVISION NOTES
April 2022 * Initial release

5 Device Comparison Table

Device Orderable Part Number Rated Output Current Junction Temperature Range External Sync(1)
TLVM13620 TLVM13620RDHR 2 A –40°C to 125°C No
TLVM13630 TLVM13630RDHR 3 A –40°C to 125°C No
TLVM13640 TLVM13640RDLR 4 A –40°C to 125°C No
TLVM13660 TLVM13660RDLR 6 A –40°C to 125°C No
(1) See the TPSM63602, TPSM63603, TPSM63604, and TPSM63606 for applications that require clock synchronization, an output voltage above 6 V, spread-spectrum modulation for EMI mitigation or both.

6 Pin Configuration and Functions

Figure 6-1 20-Pin QFNRDL Package(Top View)
Table 6-1 Pin Functions
Pin Type(1) Description
Name NO.
VIN1, VIN2 1, 16 P Input supply voltage. Connect the input supply to these pins. Connect input capacitors between these pins and PGND in close proximity to the device.
SW 2 O Switch node. Do not place any external component on this pin or connect to any signal. The amount of copper placed on this pin must be kept to a minimum to prevent issues with noise and EMI.
CBOOT 3 I/O Bootstrap pin for the internal high-side gate driver. A 100-nF bootstrap capacitor is internally connected from this pin to SW within the module to provide the bootstrap voltage. CBOOT is brought out to use in conjunction with RBOOT to effectively lower the value of the internal series bootstrap resistance to adjust the switch-node slew rate, if necessary.
RBOOT 4 I/O External bootstrap resistor connection. Internal to the device, a 100-Ω bootstrap resistor is connected between RBOOT and CBOOT. RBOOT is brought out to use in conjunction with CBOOT to effectively lower the value of the internal series bootstrap resistance to adjust the switch-node slew rate, if necessary.
VLDOIN 5 P Input bias voltage. Input to the internal LDO that supplies the internal control circuits. Connect to an output voltage point to improve efficiency. Connect an optional high-quality 0.1-μF to 1-μF capacitor from this pin to ground for improved noise immunity. If the output voltage is above 12 V, connect this pin to ground.
AGND 6, 11 G Analog ground. Zero-voltage reference for internal references and logic. All electrical parameters are measured with respect to this pin. These pins must be connected to PGND. See Section 11.2 for a recommended layout.
VCC 7 O Internal LDO output. Used as a supply to the internal control circuits. Do not connect to any external loads. A 1-μF capacitor internally connects from VCC to AGND.
VOUT1, VOUT2 8, 9 P Output voltage. These pins are connected to the internal buck inductor. Connect these pins to the output load and connect external output capacitors between these pins and PGND.
FB 10 I Feedback input. Connect the midpoint of the feedback resistor divider to this pin. Connect the upper resistor (RFBT) of the feedback divider to VOUT at the desired point of regulation. Connect the lower resistor (RFBB) of the feedback divider to AGND. Do not leave open or connect to ground.
RT 12 I Frequency setting pin used to set the switching frequency between 200 kHz and 2.2 MHz by placing an external resistor from RT to AGND. Do not leave open or connect to ground.
PG 13 O Open-drain power-good monitor output that asserts low if the FB voltage is not within the specified window thresholds. A 10-kΩ to 100-kΩ pullup resistor to a suitable voltage is required. If not used, PG can be left open or connected to GND.
EN 14 I Precision enable input pin. High = on, Low = off. Can be connected to VIN. Precision enable allows the pin to be used as an adjustable input voltage UVLO. The module can be turned off by using an open-drain/collector device to connect this pin to AGND. Connect an external resistor divider between this pin, VIN and AGND to create an external UVLO.
NC 15 — No connection. Tie to GND or leave open.
PGND 17, 18, 19, 20 G Power ground. This is the return current path for the power stage of the device. Connect these pads to the input supply return, the load return, and the capacitors associated with the VIN and VOUT pins. See Section 11.2 for a recommended layout.
(1) P = Power, G = Ground, I = Input, O = Output

7 Specifications

7.1 Absolute Maximum Ratings

Limits apply over TJ = –40°C to 150°C (unless otherwise noted). (1)
MIN MAX UNIT
Input voltage VIN1, VIN2 to AGND, PGND –0.3 42 V
RBOOT to SW –0.3 5.5 V
CBOOT to SW –0.3 5.5 V
VLDOIN to AGND, PGND –0.3 min (VVIN + 0.3, 16) V
EN to AGND, PGND –0.3 42 V
RT to AGND, PGND –0.3 5.5 V
FB to AGND, PGND –0.3 16 V
PG to AGND, PGND 0 20 V
PGND to AGND –1 2 V
Output voltage
 		 VCC to AGND, PGND –0.3 5.5 V
SW to AGND, PGND(2) –0.3 42 V
VOUT1, VOUT2  to AGND, PGND –0.3 6 V
Input current PG 10 mA
TJ Junction temperature –40 150 °C
TA Ambient temperature –40 125 °C
Tstg  Storage temperature –55 150 °C
Peak reflow case temperature 250 °C
Maximum number of reflows allowed 3
Mechanical vibration MIL-STD-883D, Method 2007.2, 20 Hz to 2 kHz 20 G
Mechanical shock MIL-STD-883D, Method 2002.3, 1 ms, 1/2 sine, mounted 500 G
(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.
(2) A voltage of 2 V below PGND and 2 V above VIN can appear on this pin for ≤ 200 ns with a duty cycle of ≤ 0.01%.

7.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±1500 V
Charged-device model (CDM), per ANSI/ESDA/JEDEC JS-002(2) ±500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

Limits apply over TJ = –40°C to 125°C (unless otherwise noted).
MIN NOM MAX UNIT
Input voltage VIN (input voltage range after start-up) 3 36 V
Input voltage VLDOIN min (VVIN, 12) V
Output voltage VOUT(1) 1 6 V
Output current IOUT(2) 0 6 A
Frequency FSW set by RT  200 2200 kHz
Input current PG 2 mA
Output voltage PG 16 V
TJ Operating junction temperature –40 125 °C
TA Operating ambient temperature –40 105 °C
(1) Under no conditions should the output voltage be allowed to fall below zero volts.
(2) Maximum continuous DC current can be derated when operating with high switching frequency, high ambient temperature, or both. Refer to the Typical Characteristics section for details.

7.4 Thermal Information

THERMAL METRIC(1) RDL (QFN) UNIT
20 PINS
RθJA Junction-to-ambient thermal resistance (TLVM13660 EVM) 22.6 °C/W
RθJA Junction-to-ambient thermal resistance (2) 33.1 °C/W
ψJT Junction-to-top characterization parameter (3) 1 °C/W
ψJB Junction-to-board characterization parameter (4) 12.3 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.
(2) The junction-to-ambient thermal resistance, RθJA, applies to devices soldered directly to a 75-mm × 75-mm four-layer PCB with 2 oz. copper and natural convection cooling. Additional airflow and PCB copper area reduces RθJA. 
(3) The junction-to-top board characterization parameter, ψJT, estimates the junction temperature, TJ, of a device in a real system, using a procedure described in JESD51-2A (section 6 and 7). TJ = ψJT × PDIS + TT; where PDIS is the power dissipated in the device and TT is the temperature of the top of the device.
(4) The junction-to-board characterization parameter, ψJB, estimates the junction temperature, TJ, of a device in a real system, using a procedure described in JESD51-2A (sections 6 and 7). TJ = ψJB × PDIS + TB; where PDIS is the power dissipated in the device and TB is the temperature of the board 1mm from the device.

7.5 Electrical Characteristics

Limits apply over TJ = –40°C to 125°C, VIN = 24 V, VOUT = 3.3 V, VLDOIN = 5 V, FSW = 800 kHz (unless otherwise noted). Minimum and maximum limits are specified through production test or by design. Typical values represent the most likely parametric norm and are provided for reference only.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY VOLTAGE
VIN Input operating voltage range Needed to start up (over the IOUT range) 3.95 36 V
Once operating (over the IOUT range) 3 36 V
VIN_HYS Hysteresis(1) 1 V
IQ_VIN Input operating quiescent current (non-switching)  TA = 25°C, VEN = 3.3 V, VFB = 1.5 V 7 µA
ISDN_VIN VIN shutdown quiescent current VEN = 0 V, TA = 25°C 1 µA
ENABLE
VEN_RISE EN voltage rising threshold 1.161 1.263 1.365 V
VEN_FALL EN voltage falling threshold 0.91 V
VEN_HYS EN voltage hysteresis  0.303 0.353 0.404 V
VEN_WAKE EN wake-up threshold 0.4 V
IEN Input current into EN (non-switching) VEN = 3.3 V, VFB = 1.5 V 10 nA
tEN EN high to start of switching delay(1) 0.7 ms
VCC INTERNAL LDO
VCC Internal LDO VCC voltage 3.4 V ≤ VVLDOIN ≤ 12.5 V 3.3 V
VVLDOIN = 3.1 V, non-switching 3.1 V
VCC_UVLO VCC UVLO rising threshold VVLDOIN < 3.1 V(1) 3.6 V
VIN < 3.6 V(2) 3.6 V
VCC_UVLO_HYS VCC UVLO hysteresis(2) Hysteresis below VCC_UVLO 1.1 V
IVLDOIN Input current into VLDOIN pin (non-switching)(3) VEN = 3.3 V, VFB = 1.5 V 25 31 µA
FEEDBACK
VOUT Adjustable output voltage range Over the IOUT range 1 6 V
VFB Feedback voltage TA = 25°C, IOUT = 0 A 1.0 V
VFB_ACC Feedback voltage accuracy Over the VIN range, VOUT = 1 V, IOUT = 0 A, FSW = 200 kHz –1% +1%
VFB Load regulation TA = 25°C, 0 A ≤ IOUT ≤ 6 A 0.1%
VFB Line regulation TA = 25°C, IOUT = 0 A, 4 V ≤ VIN ≤ 36 V 0.1%
IFB Input current into FB  VFB = 1 V 10 nA
CURRENT
IOUT Output current TA = 25°C 0 6 A
IOCL Output overcurrent (DC) limit threshold 8.3 A
IL_HS High-side switch current limit Duty cycle approaches 0% 8.3 9.3 10.3 A
IL_LS Low-side switch current limit 6.5 7.1 7.7 A
IL_NEG Negative current limit  –3 A
VHICCUP Ratio of FB voltage to in-regulation FB voltage to enter hiccup Not during soft start 40%
tW Short circuit wait time ("hiccup" time before soft start)(1) 80 ms
SOFT START
tSS Time from first SW pulse to VFB at 90% VIN ≥ 4.2 V 3.5 5 7 ms
tSS2 Time from first SW pulse to release of FPWM lockout if output not in regulation(1) VIN ≥ 4.2 V 9.5 13 17 ms
POWER GOOD
PGOV PG upper threshold – rising % of VOUT setting 105% 107% 110%
PGUV PG lower threshold – falling % of VOUT setting 92% 94% 96.5%
PGHYS PG threshold hysteresis (rising and falling) % of VOUT setting 1.3%
VIN_PG_VALID Input voltage for valid PG output 46-μA pullup, VEN = 0 V 1.0 V
VPG_LOW PG low-level output voltage 2-mA pullup to PG pin, VEN = 3.3 V 0.4 V
IPG Input current into PG pin when open drain output is high VPG = 3.3 V 10 nA
IOV Pulldown current at the SW node during an overvoltage condition 0.5 mA
tPG_FLT_RISE Delay time to PG high signal 1.5 2.0 2.5 ms
tPG_FLT_FALL Glitch filter time constant for PG function 120 µs
SWITCHING FREQUENCY
fSW_RANGE Switching frequency range by RT or SYNC 200 2200 kHz
fSW_RT1 Default switching frequency by RRT RRT = 66.5 kΩ 180 200 220 kHz
fSW_RT2 Default switching frequency by RRT RRT = 5.76 kΩ 1980 2200 2420 kHz
SYNCHRONIZATION
tB Blanking of EN after rising or falling edges(1) 4 28 µs
POWER STAGE
VBOOT_UVLO Voltage on CBOOT pin relative to SW that turns off the high-side switch 2.1 V
tON(min) Minimum ON pulse width(1) VOUT = 1 V, IOUT = 1 A, RBOOT shorted to CBOOT 55 70 ns
tON(max) Maximum ON pulse width(1) 9 µs
tOFF(min) Minimum OFF pulse width VIN = 4 V, IOUT = 1 A, RBOOT shorted to CBOOT 65 85 ns
THERMAL SHUTDOWN
TSHD Thermal shutdown threshold (1) Temperature rising 158 168 180 °C
TSHD-HYS Thermal shutdown hysteresis (1) 10 °C
(1) Parameter specified by design, statistical analysis and production testing of correlated parameters. Not production tested.
(2) Production tested with VIN = 3 V.
(3) This is the current used by the device while not switching, open loop, with FB pulled to +5% of nominal. It does not represent the total
input current to the system while regulating.

 
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