The TMAG5170 performs mandatory CRC for SPI communication. The Data integrity is maintained in both directions by a 4-bit CRC covering the content of the incoming and outgoing 32-bit messages. The four LSB bits of each 32-bit SPI frame are dedicated for the CRC. The CRC code is generated by the polynomial x⁴ + x + 1. Initialize the CRC bits with b1111.

During the SDI write frame, the TMAG5170 reads for the CRC data before executing a write instruction. The write instruction from the controller is ignored if there is any CRC error present in the frame. During the SDI regular read frame, the TMAG5170 starts to deliver the requested data through SDO line in the same frame and notifies the controller of any error occurrence through the ERROR_STAT bit. If the device detects a CRC error in the SDI line, the device will invert the last bit of the SDO CRC in the same frame to promptly signal to a controller that the SPI communication is compromised. A controller can also determine the presence of a CRC error in the SDI frame by checking the Status11 bit in the next regular read frame.

Figure 7-13 4-Bit CRC Calculation

Use the following XOR function equations to calculate the 4-bit CRC. Figure 7-13 describes the notations of these equations.

The following shows example codes for calculating the 4-bit CRC.

function logic [3:0] calculate_crc4;
   input logic [27:0] frame;

   logic [31:0]       padded_frame;
   logic [3:0] 	      frame_crc;
   logic 	      inv;
   integer 	      i;

   padded_frame = {frame, 4'b0000};
   
   begin
      frame_crc = 4'hf; // initial value
      for (i=31; i >= 0; i=i-1) begin
	 inv = padded_frame[i] ^ frame_crc[3];
	 frame_crc[3] = frame_crc[2];
	 frame_crc[2] = frame_crc[1];
	 frame_crc[1] = frame_crc[0] ^ inv;
	 frame_crc[0] = inv;
      end
      return frame_crc;
   end
endfunction