JAJSP27A September   2022  – September 2023 TMAG5173-Q1

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics
    6. 6.6  Temperature Sensor
    7. 6.7  Magnetic Characteristics For A1, B1, C1, D1
    8. 6.8  Magnetic Characteristics For A2, B2, C2, D2
    9. 6.9  Magnetic Temp Compensation Characteristics
    10. 6.10 I2C Interface Timing
    11. 6.11 Power up Timing
    12. 6.12 Timing Diagram
    13. 6.13 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Magnetic Flux Direction
      2. 7.3.2 Sensor Location
      3. 7.3.3 Interrupt Function
      4. 7.3.4 Device I2C Address
      5. 7.3.5 Magnetic Range Selection
      6. 7.3.6 Update Rate Settings
    4. 7.4 Device Functional Modes
      1. 7.4.1 Standby (Trigger) Mode
      2. 7.4.2 Sleep Mode
      3. 7.4.3 Continuous Measure Mode
    5. 7.5 Programming
      1. 7.5.1 I2C Interface
        1. 7.5.1.1 SCL
        2. 7.5.1.2 SDA
        3. 7.5.1.3 I2C Read/Write
          1. 7.5.1.3.1 Standard I2C Write
          2. 7.5.1.3.2 General Call Write
          3. 7.5.1.3.3 Standard 3-Byte I2C Read
          4. 7.5.1.3.4 1-Byte I2C Read Command for 16-Bit Data
          5. 7.5.1.3.5 1-Byte I2C Read Command for 8-Bit Data
          6. 7.5.1.3.6 I2C Read CRC
      2. 7.5.2 Data Definition
        1. 7.5.2.1 Magnetic Sensor Data
        2. 7.5.2.2 Temperature Sensor Data
        3. 7.5.2.3 Angle and Magnitude Data Definition
        4. 7.5.2.4 Magnetic Sensor Offset Correction
    6. 7.6 TMAG5173-Q1 Registers
  9. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Select the Sensitivity Option
      2. 8.1.2 Temperature Compensation for Magnets
      3. 8.1.3 Sensor Conversion
        1. 8.1.3.1 Continuous Conversion
        2. 8.1.3.2 Trigger Conversion
        3. 8.1.3.3 Pseudo-Simultaneous Sampling
      4. 8.1.4 Magnetic Limit Check
      5. 8.1.5 Magnetic Threshold Band Cross Detection
      6. 8.1.6 Error Calculation During Linear Measurement
      7. 8.1.7 Error Calculation During Angular Measurement
    2. 8.2 Typical Applications
      1. 8.2.1 Angle Measurement
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1 Gain Adjustment for Angle Measurement
        3. 8.2.1.3 Application Curves
      2. 8.2.2 I2C Address Expansion
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
    3. 8.3 Best Design Practices
    4. 8.4 Power Supply Recommendations
    5. 8.5 Layout
      1. 8.5.1 Layout Guidelines
      2. 8.5.2 Layout Example
  10. 9 デバイスおよびドキュメントのサポート
    1. 9.1 ドキュメントのサポート
      1. 9.1.1 Related Documentation
    2. 9.2 ドキュメントの更新通知を受け取る方法
    3. 9.3 サポート・リソース
    4. 9.4 商標
    5. 9.5 静電気放電に関する注意事項
    6. 9.6 用語集
  11. 10Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.3.3 Interrupt Function

The TMAG5173-Q1 supports flexible and configurable interrupt functions through either the INT or the SCL pin. Table 7-1 shows different conversion completion events where result registers and SET_COUNT bits update, and where they do not.

Table 7-1 Result Register & SET_COUNT Update After Conversion Completion
INT_MODEMODE DESCRIPTIONI2C BUS BUSY, NOT TALKING TO DEVICEI2C BUS BUSY & TALKING TO DEVICEI2C BUS NOT BUSY
RESULT UPDATE?SET_COUNT UPDATE?RESULT UPDATE?SET_COUNT UPDATE?RESULT UPDATE?SET_COUNT UPDATE?
000b No interrupt Yes Yes No No Yes Yes
001b Interrupt through INT Yes Yes No No Yes Yes
010b Interrupt through INT except when I2C busy Yes Yes No No Yes Yes
011b Interrupt through SCL Yes Yes No No Yes Yes
100b Interrupt through SCL except when I2C busy No No No No Yes Yes
Note:

TI does not recommend sharing the same I2C bus with multiple secondary devices when using the SCL pin for interrupt function. The SCL interrupt may corrupt transactions with other secondary devices if present in the same I2C bus.

7.3.3.1 Interrupt Through SCL

Figure 7-3 shows an example for interrupt function through the SCL pin with the device programmed to generate interrupt at magnetic threshold cross event. When the magnetic threshold cross is detected, the device asserts a fixed width interrupt signal through the SCL pin.

TMAG5173-Q1 Interrupt Through SCL Figure 7-3 Interrupt Through SCL

7.3.3.2 Fixed Width Interrupt Through INT

Figure 7-4 shows an example for fixed-width interrupt function through the INT pin. The device is programmed to generate interrupt at magnetic threshold cross event. The INT_STATE register bit is set 1b. When the magnetic threshold cross is detected, the device asserts a fixed width interrupt signal through the INT pin.

TMAG5173-Q1 Fixed Width Interrupt Through INT Figure 7-4 Fixed Width Interrupt Through INT

7.3.3.3 Latched Interrupt Through INT

Figure 7-5 shows an example for latched interrupt function through the INT pin. The device is programmed to generate interrupt at magnetic threshold cross event. The INT_STATE register bit is set 0b. When the magnetic threshold cross is detected, the device asserts a latched interrupt signal through the INT pin. The latched interrupt is cleared only after the device receives a valid address through the SCL line.

TMAG5173-Q1 Latched Interrupt Through INT Figure 7-5 Latched Interrupt Through INT