JAJSQR0C July   2023  – January 2025 TMCS1123

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Device Comparison
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Insulation Specifications
    6. 6.6 Electrical Characteristics
    7. 6.7 Typical Characteristics
  8. 7 Parameter Measurement Information
    1. 7.1 Accuracy Parameters
      1. 7.1.1 Sensitivity Error
      2. 7.1.2 Offset Error and Offset Error Drift
      3. 7.1.3 Nonlinearity Error
      4. 7.1.4 Power Supply Rejection Ratio
      5. 7.1.5 Common-Mode Rejection Ratio
      6. 7.1.6 External Magnetic Field Errors
    2. 7.2 Transient Response Parameters
      1. 7.2.1 CMTI, Common-Mode Transient Immunity
    3. 7.3 Safe Operating Area
      1. 7.3.1 Continuous DC or Sinusoidal AC Current
      2. 7.3.2 Repetitive Pulsed Current SOA
      3. 7.3.3 Single Event Current Capability
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Current Input
      2. 8.3.2 Input Isolation
      3. 8.3.3 Ambient Field Rejection
      4. 8.3.4 High-Precision Signal Chain
        1. 8.3.4.1 Temperature Stability
        2. 8.3.4.2 Lifetime and Environmental Stability
      5. 8.3.5 Internal Reference Voltage
      6. 8.3.6 Current-Sensing Measurable Ranges
      7. 8.3.7 Overcurrent Detection
        1. 8.3.7.1 Setting The User Configurable Overcurrent Threshold
          1. 8.3.7.1.1 Setting Overcurrent Threshold Using Power Supply Voltage
          2. 8.3.7.1.2 Setting Overcurrent Threshold Using Internal Reference Voltage
          3. 8.3.7.1.3 Setting Overcurrent Threshold Example
        2. 8.3.7.2 Overcurrent Output Response
        3. 8.3.7.3 Overcurrent Detection MASK Time
      8. 8.3.8 Sensor Diagnostics
        1. 8.3.8.1 Thermal Alert
        2. 8.3.8.2 Sensor Alert
    4. 8.4 Device Functional Modes
      1. 8.4.1 Power-Down Behavior
  10. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Total Error Calculation Examples
        1. 9.1.1.1 Room-Temperature Error Calculations
        2. 9.1.1.2 Full-Temperature Range Error Calculations
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curve
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Device Nomenclature
    2. 10.2 Device Support
      1. 10.2.1 Development Support
    3. 10.3 Documentation Support
      1. 10.3.1 Related Documentation
    4. 10.4 ドキュメントの更新通知を受け取る方法
    5. 10.5 サポート・リソース
    6. 10.6 Trademarks
    7. 10.7 静電気放電に関する注意事項
    8. 10.8 用語集
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

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発注情報

6.5 Insulation Specifications

PARAMETER TEST CONDITIONS VALUE UNIT
GENERAL
CLR External clearance(1) Shortest terminal-to-terminal distance through air ≥ 8 mm
CPG External creepage(1) Shortest terminal-to-terminal distance across the package surface ≥ 8 mm
CTI Comparative tracking index DIN EN 60112; IEC 60112 ≥ 600 V
Material group According to IEC 60664-1 I
Overvoltage category per IEC 60664-1 Rated mains voltage ≤ 600VRMS I-IV
VIORM Maximum repetitive peak isolation voltage AC voltage (bipolar) 1697 VPK
VIOWM Maximum reinforced isolation working voltage AC voltage (sine wave); Time Dependent Dielectric Breakdown (TDDB) test, < 1ppm fail rate, see Input Isolation section 10year lifetime 950 VRMS
1343 VDC
Maximum basic isolation working voltage AC voltage (sine wave); Time Dependent Dielectric Breakdown (TDDB) test, < 1000ppm fail rate, see Input Isolation section 10year lifetime 1200 VRMS
1697 VDC
VIOTM Maximum transient isolation voltage VTEST = √2 x VISO, t = 60s (qualification);
VTEST = 1.2 × VIOTM, t = 1s (100% production)		 7071 VPK
VIOSM Maximum surge isolation voltage(2) Test method per IEC 62368-1, 1.2/50µs waveform,
VTEST = 1.3 × VIOSM (qualification)		 10000 VPK
qpd Apparent charge(3) Method b1: At routine test (100% production) and preconditioning (type test), Vini = 1.2 x VIOTM, tini = 1s, Vpd(m) = 1.875 × VIORM, tm = 1s ≤5 pC
CIO Barrier capacitance, input to output(4) VIO = 0.4 sin (2πft), f = 1MHz 0.6 pF
RIO Isolation resistance, input to output(4) VIO = 500V, TA = 25°C >1012 Ω
VIO = 500V, 100°C ≤ TA ≤ 125°C >1011 Ω
VIO = 500V at TS = 150°C >109 Ω
Pollution degree 2
UL 1577
VISO Withstand isolation voltage VTEST = VISO, t = 60s (qualification);
VTEST = 1.2 × VISO, t = 1s (100% production)		 5000 VRMS
(1) Apply creepage and clearance requirements according to the specific equipment isolation standards of an application. Take care to maintain the creepage and clearance distance of the board design to make sure that the mounting pads of the isolator on the printed circuit board do not reduce this distance. Creepage and clearance on a printed circuit board become equal in certain cases. Techniques such as inserting grooves, ribs, or both on a printed circuit board are used to help increase these specifications.
(2) Testing is carried out in air or oil to determine the intrinsic surge immunity of the isolation barrier.
(3) Apparent charge is electrical discharge caused by a partial discharge (pd).
(4) All pins on each side of the barrier tied together creating a two-terminal device.