JAJSOZ7A August 2022 – April 2024 TMDS1204
PRODUCTION DATA
PIN | TYPE(1) | DESCRIPTION | |
---|---|---|---|
NAME | NO. | ||
VCC | 1 | P | 3.3V power supply |
RCLKOUTp | 2 | O | HDMI 1.4/2.0 clock differential positive output when not operating in HDMI 2.1 FRL mode with Fan-out buffer feature enabled. External AC coupling required. If not used, then this pin can be left unconnected. |
RCLKOUTn | 3 | O | HDMI 1.4/2.0 clock differential negative output when not operating in HDM I2.1 FRL mode with Fan-out buffer feature enabled. External AC coupling required. If not used, then this pin can be left unconnected. |
CTLEMAP_SEL | 4 | I 4 Level (PU/PD) |
CTLE Map select. When TMDS1204 is configured in pin-strap mode, this pin selects the CTLE Map used. Table 7-8 provides more details. Also in pin-strap this pin will control whether or not AEQ is enabled. Table 7-9 provides more details. In I2C mode, CTLE Map and AEQ enable is determined by registers. |
LINEAR_EN | 5 | I 4-Level (PU/PD) |
In pin-strap mode, selects whether TMDS1204 operates in linear or limited redriver mode. Table 7-5 provides more details. |
VCC | 6 | P | 3.3V power supply |
EN | 7 | I 2-Level (PU) |
When low, TMDS1204 will be held in reset. The IN_D[2:0], IN_CLK, OUT_D[2:0] and OUT_CLK pins will be held in high impedance while EN is low. On rising edge of EN, device will sample four-level inputs and function based on the sampled state of the pins. This pin has a internal 250 k pull-up to VIO. |
EQ1 | 8 | I 4 Level (PU/PD) |
EQ1 Pin Setting when TMDS1204 is configured for pin strap mode; Works in conjunction with EQ0; Table 7-6 provides the settings. In I2C mode, EQ settings are controlled through registers. |
IN_CLKn | 9 | I | Clock differential negative input. |
IN_CLKp | 10 | I | Clock differential positive input. |
HPD_OUT | 11 | O | Hot plug detect output to source side. If not used, then this pin can be left floating. |
IN_D0n | 12 | I | Channel 0 differential negative input. |
IN_D0p | 13 | I | Channel 0 differential positive input. |
VIO | 14 | P | Voltage supply for I/Os. Table 7-2 provides more information. |
IN_D1n | 15 | I | Channel 1 differential negative input. |
IN_D1p | 16 | I | Channel 1 differential positive input. |
MODE | 17 | I 4 Level (PU/PD) |
Mode control pin. Selects between pin-strap and I2C mode. For more information, refer to Section 7.3.1. |
IN_D2n | 18 | I | Channel 2 differential negative input. |
IN_D2p | 19 | I | Channel 2 differential positive input. |
VCC | 20 | P | 3.3V power supply. |
SCL/CFG0 | 21 | I | I2C Clock/CFG0: when TMDS1204 is configured for I2C mode, this pin will function as the I2C clock. Otherwise, this pin will function as CFG0. Table 7-18 provides more details. |
SDA/CFG1 | 22 | I/O | I2C Data / CFG1: When TMDS1204 is configured for I2C mode, this pin will function as the I2C clock. Otherwise, this pin will function as CFG1. Table 7-19 provides more details. |
AC_EN | 23 | I 2-Level (PD) |
In pin-strap mode, selects whether high speed
transmitters are externally AC or DC coupled. 0: DC-coupled 1: AC-coupled |
LV_DDC_SCL | 24 | I/O | Low voltage side DDC clock line. Internally pulled-up to VIO. |
LV_DDC_SDA | 25 | I/O | Low voltage side DDC data line. Internally pulled-up to VIO. |
SIGDET_OUT | 26 | O | SIGDET_OUT. Open drain output asserted low when signal is detected on IN_CLK or IN_D2 when HPD_IN is high. Otherwise signal is de-asserted. When used requires 10k or greater pull-up resistor. |
DCGAIN | 27 | I 4 Level (PU/PD) |
DC Gain. "0": −3dB "R": −3dB "F": 0dB "1": +1dB |
VCC | 28 | P | 3.3V power supply |
TXPRE | 29 | I 4 Level (PU/PD) |
TX pre-emphasis control: in pin-strap mode with limited enabled, this pin controls TX EQ. In pin-strap with linear and AEQ enabled, this pin will adjust the adapted value. Table 7-15 provides the available TXPRE settings when operating in pin strap mode. In I2C mode, Tx pre-emphasis is controlled through registers. |
OUT_D2p | 30 | O | TMDS data 2 differential positive output |
OUT_D2n | 31 | O | TMDS data 2 differential negative output |
HPD_IN | 32 | I 2-Level (PD) |
Hot plug detect input from sink side. This pin has an internal pull-down resistor and is fail-safe. |
OUT_D1p | 33 | O | TMDS data 1 differential positive output |
OUT_D1n | 34 | O | TMDS data 1 differential negative output |
ADDR/EQ0 | 35 | I 4 Level (PU/PD) |
Address bit for I2C programming when TMDS1204 is configured for I2C mode. Table 7-22 provides more details. EQ0 pin setting when TMDS1204 is configured for pin strap mode; works in conjunction with EQ1; Table 7-6 lists the settings. In I2C mode, EQ settings are controlled through registers. |
OUT_D0p | 36 | O | TMDS data 0 differential positive output |
OUT_D0n | 37 | O | TMDS data 0 differential negative output |
TXSWG | 38 | I 4 Level (PU/PD) |
TX output swing control: 4 settings. This pin is only used in pin strap mode. Table 7-17 provides the available TX swing settings. In I2C mode, TX output swing is controlled through registers. |
OUT_CLKp | 39 | O | TMDS data clock differential positive output |
OUT_CLKn | 40 | O | TMDS data clock differential negative output |
Thermal Pad | — | Thermal pad. Connect to a solid ground plane. |