JAJS306I August 2007 – June 2024 TMP102
PRODUCTION DATA
The device that initiates the transfer is called a controller, and the devices controlled by the controller are called targets. The bus must be controlled by a controller device that generates the serial clock (SCL), controls the bus access, and generates the START and STOP conditions.
To address a specific device, a START condition is initiated, indicated by pulling the data-line (SDA) from a high to low logic level when SCL is high. All targets on the bus shift in the target address byte on the rising edge of the clock, with the last bit indicating whether a read or write operation is intended. During the ninth clock pulse, the target being addressed responds to the controller by generating an acknowledge and by pulling SDA pin low.
A data transfer is then initiated and sent over eight clock pulses followed by an acknowledge bit. During the data transfer the SDA pin must remain stable when SCL is high, because any change in SDA pin when SCL pin is high is interpreted as a START signal or STOP signal.
When all data have been transferred, the controller generates a STOP condition indicated by pulling SDA pin from low to high, when the SCL pin is high.