JAJSLQ4C May   2021  – June 2022 TMP126-Q1

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Device Comparison
  6. 6 Pin Configuration and Functions
  7. 7 仕様
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 SPI Interface Timing
    7. 7.7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Descriptions
      1. 8.3.1 Temperature Limits
      2. 8.3.2 Slew Rate Warning
      3. 8.3.3 Cyclic Redundancy Check (CRC)
      4. 8.3.4 NIST Traceability
      5. 8.3.5 Fast Measurement Intervals With No Self-Heating Concerns
    4. 8.4 Device Functional Modes
      1. 8.4.1 Continuous Conversion Mode
      2. 8.4.2 Shutdown Mode
      3. 8.4.3 One-Shot Mode
      4. 8.4.4 Interrupt and Comparator Mode
        1. 8.4.4.1 Interrupt Mode
        2. 8.4.4.2 Comparator Mode
    5. 8.5 Programming
      1. 8.5.1 Temperature Data Format
      2. 8.5.2 Serial Bus Interface
        1. 8.5.2.1 Command Word Structure
          1. 8.5.2.1.1 Don't Care
          2. 8.5.2.1.2 CRC Enable
          3. 8.5.2.1.3 CRC Data Block Length
          4. 8.5.2.1.4 Auto Increment
          5. 8.5.2.1.5 Read/Write
          6. 8.5.2.1.6 Sub-Address
        2. 8.5.2.2 Communication
        3. 8.5.2.3 Write Operations
        4. 8.5.2.4 Read Operations
        5. 8.5.2.5 Cyclic Redundancy Check (CRC)
          1. 8.5.2.5.1 Cyclic Redundancy Check Implementation
    6. 8.6 Register Map
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 サポート・リソース
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

8.6 Register Map

Table 8-3 TMP126-Q1 Registers
ADDRESS TYPE RESET ACRONYM REGISTER NAME SECTION
00h R 0000h Temp_Result Temperature result register Go
01h R 0000h Slew_Result Slew rate result register Go
02h R/RC 0000h Alert_Status Alert status register Go
03h R/W 0006h Configuration Configuration register Go
04h R/W 0016h Alert_Enable Alert enable register Go
05h R/W F380h TLow_Limit Temperature low limit register Go
06h R/W 2A80h THigh_Limit Temperature high limit register Go
07h R/W 0A0Ah Hysteresis Hysteresis register Go
08h R/W 0500h Slew_Limit Temperature slew rate limit register Go
09h R xxxxh Unique_ID1 Unique ID1 register Go
0Ah R xxxxh Unique_ID2 Unique ID2 register Go
0Bh R xxxxh Unique_ID3 Unique ID3 register Go
0Ch R 2126h Device_ID Device ID register Go
10h-2Ah R xxxxh Reserved Reserved
Table 8-4 TMP126-Q1 Access Type Codes
Access Type Code Description
Read Type
R R Read
RC R
C		 Read
to Clear
R-0 R
-0		 Read
Returns 0s
Write Type
W W Write
Reset or Default Value
-n Value after reset or the default value

8.6.1 Temp_Result Register (Address = 00h) [reset = 0000h]

This register stores the latest temperature conversion result in a 14-bit two's complement format with a LSB (Least Significant Bit) equal to 0.03125°C.

Return to Register Map.

Figure 8-19 Temp_Result Register
15 14 13 12 11 10 9 8
Temp_Result[13:6]
R-00h
7 6 5 4 3 2 1 0
Temp_Result[5:0] Reserved
R-00h R-00b
Table 8-5 Temp_Result Register Field Descriptions
Bit Field Type Reset Description
15:2 Temp_Result[13:0] R 0000h 14-bit temperature conversion result.

Temperature data is represented by a 14-bit, two's complement word with an LSB (Least Significant Bit) equal to 0.03125°C.
1:0 Reserved R 00b These two bits will always read 00b

8.6.2 Slew_Result Register (Address = 01h) [reset = 0000h]

This register shows the latest slew rate calculation. Two consecutive measurements in continuous conversion mode are required before a result is shown. When not in continuous conversion mode the register will return to the default value.

The slew rate result is depicted in 14-bit twos-complement format with the LSB equal to 0.03125°C/s. The TMP126 does not accurately report negative slew rate values and bit 13 of the output result can be used to indicate a negative slew rate but the output value cannot be guaranteed.

Return to Register Map.

Figure 8-20 Slew_Result Register
15 14 13 12 11 10 9 8
Slew_Rate_Result[13:6]
R-00h
7 6 5 4 3 2 1 0
Slew_Rate_Result[5:0] Reserved
R-00h R-00b
Table 8-6 Slew_Result Register Field Descriptions
Bit Field Type Reset Description
15:2 Slew_Rate_Result[13:0] R 0000h Temperature slew rate result.

Temperature slew rate is represented by a 14-bit, twos-complement word with an LSB (Least Significant Bit) equal to 0.03125°C/s. Format is°C/s.

1:0 Reserved R 00b Reserved

8.6.3 Alert_Status Register(Address = 02h) [reset = 0000h]

This register show the current alert status of the TMP126-Q1. This register will currently only clear with a single register read without auto increment.

Return to Register Map.

Figure 8-21 Alert_Status Register
15 14 13 12 11 10 9 8
Reserved
R-00h
7 6 5 4 3 2 1 0
CRC_Flag Slew_Status Slew_Flag THigh_Status TLow_Status THigh_Flag TLow_Flag Data_Ready_Flag
RC-0b R-0b RC-0b R-0b R-0b RC-0b RC-0b RC-0b
Table 8-7 Alert_Status Register Field Descriptions
Bit Field Type Reset Description
15:8 Reserved R 00h Reserved
7 CRC_Flag RC 0b CRC checksum error flag indicator. This indicates that the write transaction CRC checksum failed and the register settings were discarded.

0b = The most recent CRC enabled write transaction was successful.

1b = The most recent CRC enabled write transaction failed.
6 Slew_Pos_Status R 0b Positive slew rate status indicator. This bit is set if there is a positive slew rate exceeding the Slew_Rate_Limit.

0b: The most recent temperature conversion result is below the Slew_Rate_Limit.

1b: The most recent temperature conversion result is above the Slew_Rate_Limit.
5 Slew_Flag RC 0b Slew rate flag indicator. This indicates that the current there was a temperature slew rate beyond the slew rate limit threshold. Reading Alert_Status register will clear this bit.

0b = The most recent temperature conversion has not crossed the Slew_Rate_Limit threshold.

1b = A temperature conversion has crossed the Slew_Rate_Limit threshold.
4 THigh_Status R 0b High temperature status indicator.

0b: The most recent temperature conversion result is below the Thigh_Limit

1b: The most recent temperature conversion is above the THigh_Limit. Once set, this bit will not clear until a temperature conversion is below THigh_Limit - THigh_Hyst
3 TLow_Status R 0b Low temperature status indicator.

0b: The most recent temperature conversion result is above the TLow_Limit

1b: The most recent temperature conversion is below the THigh_Limit. Once set, this bit will not clear until a temperature conversion is above TLow_Limit + TLow_Hyst
2 THigh_Flag RC 0b High temperature flag indicator. This indicates that the latest temperature conversion has cross above the THigh_Limit register threshold or crossed below the THigh_Limit - THigh_Hyst threshold. Reading Alert_Status register will clear this bit.

0b = The most recent temperature conversion has not crossed the THigh_Limit or the hysteresis threshold.

1b: A temperature conversion crossed the THigh_Limit or crossed below the THigh_Limit - THigh_Hyst threshold. Once the THigh_Flag is set, THigh_Flag will not be set again until a temperature conversion is below THigh_Limit - THigh_Hyst
1 TLow_Flag RC 0b Low temperature flag indicator. This indicates that the latest temperature conversion has cross below the TLow_Limit register threshold or crossed above the Tlow_Limit + TLow_Hyst threshold. Reading Alert_Status register will clear this bit.

0b = The most recent temperature conversion has not crossed the TLow_Limit or the hysteresis threshold.

1b: A temperature conversion crossed below the TLow_Limit. Once the TLow_Flag is set, TLow_Flag will not be set again until temperature conversion is above TLow_Limit + TLow_Hyst
0 Data_Ready_Flag RC 0b Data Ready flag indicator. This indicates that there is an unread temperature conversion. Reading Alert_Status register or the Temperature Results register will clear this bit.

0b = Data in Temp_Result has been read already

1b = Data in Temp_Result is unread

8.6.4 Configuration Register (Address = 03h) [reset = 0006h]

This register is used to configuration the operation of the TMP126-Q1.

Return to Register Map.

Figure 8-22 Configuration Register
15 14 13 12 11 10 9 8
Reserved Reset
R-00h R/W-0b
7 6 5 4 3 2 1 0
AVG Reserved Int_Comp One_Shot Mode Conv_Period[2:0]
R/W-0b R-0b R/W-0b R/W-0b R/W-0b R/W-110b
Table 8-8 Configuration Register Field Descriptions
Bit Field Type Reset Description
15:9 Reserved R 00h Reserved
8 Resets R/W 0b Software reset bit.

When set to 1b it triggers software reset with a duration of 0.5 ms.

This bit will always read back 0b
7 AVG R/W 0b Averaging enable bit. Averaging will force every measurement including one-shot measurements to be averaged with eight conversions.

0b: Averaging is disabled

1b: Averaging is enabled
6 Reserved R 0b Reserved
5 Int_Comp R/W 0b Interrupt or comparator mode select

0b = Interrupt mode

1b = Comparator mode
4 One_Shot R/W 0b One-shot conversion trigger. Triggering a one-shot conversion will place the TMP126-Q1 into shutdown mode after the conversion completes. This bit will always read 0h.

0b = Default

1b = Trigger a one-shot conversion
3 Mode R/W 0b Conversion mode selection bit.

0b = Continuous conversion mode

1b = Shutdown mode
2:0 Conv_Period[2:0] R/W 110b Conversion period setting. This bit field changes the conversion period of the TMP126-Q1.

000b = 6 ms

001b = 31.25 ms / 32 Hz

010b = 62.5 ms / 16 Hz

011b = 125 ms / 8 Hz

100b = 250 ms / 4 Hz

101b = 500 ms / 2 Hz

110b = 1 s / 1 Hz

111b = 2 s / 0.5 Hz

8.6.5 Alert_Enable Register(Address = 04h) [reset = 0016h]

This register configures which flags of the Alert_Status register are enabled or disabled. Disabling an Alert flag will cause the ALERT pin to not assert when that flag bit is set. If the flag is enabled the ALERT pin will assert when that flag is set. The flag bit will still be set in the register when the Alert functionality is disabled for that bit.

Currently if there is an active alert on the ALERT pin and the enable for that alert is set to 0b, the TMP126-Q1 will not the de-assert the pin until the status register is read or a new conversion occurs.

Return to Register Map.

Figure 8-23 Alert_Enable Register
15 14 13 12 11 10 9 8
Reserved
R-00h
7 6 5 4 3 2 1 0
Reserved CRC_Alert_En Slew_Alert_En THigh_Alert_En TLow_Alert_En Data_Ready_Alert_En
R-000b R/W-1b R/W-0b R/W-1b R/W-1b R/W-0b
Table 8-9 Alert_Enable Register Field Descriptions
Bit Field Type Reset Description
15:5 Reserved R 000h Reserved
4 CRC_Alert_En R/W 1b Enables the CRC_Flag alert to assert the ALERT pin.

0b = CRC_Flag ALERT disabled

1b = CRC_Flag ALERT enabled
3 Slew_Alert_En R/W 0b Enables the Slew_Flag assert the ALERT pin while in interrupt mode. When in comparator mode, enables the Slew_Status to assert the ALERT.

0b = Slew_Flag ALERT disabled

1b = Slew_Flag ALERT enabled
2 THigh_Alert_En R/W 1b Enables the THigh_Flag assert the ALERT pin while in interrupt mode. When in comparator mode, enables the THigh_Status to assert the ALERT.

0b = THigh_Flag Alert disabled

1b = THigh_Flag Alert enabled
1 TLow_Alert_En R/W 1b Enables the TLow_Flag assert the ALERT pin while in interrupt mode. When in comparator mode, enables the TLow_Status to assert the ALERT.

0b = TLow_Flag Alert disabled

1b = TLow_Flag Alert enabled
0 Data_Ready_Alert_En R/W 0b Enables the Data_Ready_Flag to assert the ALERT pin.

0b = Data_Ready Alert disabled

1b = Data_Ready Alert enabled

8.6.6 TLow_Limit Register(Address = 05h) [reset = F380h]

This register is used to configuration the low temperature limit of the TMP126-Q1. The limit is formatted in a 14-bit two's complement format with a LSB (Least Significant Bit) equal to 0.03125°C. This is the same format as the TEMP_RESULT register. The range of the register is ±256°C. The default value on start-up is F380h or -25°C. If the THigh_Limit register is equal to or less than the TLow_Limit register the temperature limits will be ignored until configured such that THigh_Limit is greater than TLow_Limit.

Return to Register Map.

Figure 8-24 TLow_Limit Register
15 14 13 12 11 10 9 8
TLow_Limit[13:6]
R/W-F3h
7 6 5 4 3 2 1 0
TLow_Limit[5:0] Reserved
R/W-20h R-00b
Table 8-10 TLow_Limit Register Field Descriptions
Bit Field Type Reset Description
15:2 TLow_Limit[13:0] R/W 3CE0h 14-bit temperature low limit setting.

Temperature low limit is represented by a 14-bit, two's complement word with an LSB (Least Significant Bit) equal to 0.03125°C. The default setting for this is -25°C.
1:0 Reserved R 00b These two bits will always read 00b

8.6.7 THigh_Limit Register(Address = 06h) [reset = 2A80h]

This register is used to configuration the high temperature limit of the TMP126-Q1. The limit is formatted in a 14-bit two's complement format with a LSB (Least Significant Bit) equal to 0.03125°C. This is the same format as the Temp_Result register. The range of the register is ±256°C. The default value on start-up is 2A80h or 85°C. If the THigh_Limit register is equal to or less than the TLow_Limit register the temperature limits will be ignored until configured such that THigh_Limit is greater than TLow_Limit.

Return to Register Map.

Figure 8-25 THigh_Limit Register
15 14 13 12 11 10 9 8
THigh_Limit[13:6]
R/W-2Ah
7 6 5 4 3 2 1 0
THigh_Limit[5:0] Reserved
R/W-20h R-00b
Table 8-11 THigh_Limit Register Field Descriptions
Bit Field Type Reset Description
15:2 THigh_Limit[13:0] R/W 0AA0h 14-bit temperature high limit setting.

Temperature high limit is represented by a 14-bit, two's complement word with an LSB (Least Significant Bit) equal to 0.03125°C.
1:0 Reserved R 00b These two bits will always read 00b

8.6.8 Hysteresis Register (Address = 07h) [reset = 0A0Ah]

This register sets the hysteresis for the THigh_Limit threshold and the TLow_Limit threshold. The default hysteresis value for both the high and low limits is equal to 5 °C.

The Hysteresis is in a 8-bit unsigned format with the LSB equal to 0.5°C. This gives a maximum value of 127.5°C of hysteresis.

Return to Register Map.

Figure 8-26 Hysteresis Register
15 14 13 12 11 10 9 8
THigh_Hyst[7:0]
R/W-0Ah
7 6 5 4 3 2 1 0
TLow_Hyst[7:0]
R/W-0Ah
Table 8-12 Hysteresis Register Field Descriptions
Bit Field Type Reset Description
15:8 THigh_Hyst[7:0] R/W 0Ah THigh_Limit Hysteresis setting.

Hysteresis value is represented by a unsigned Byte with the LSB equal to 0.5°C. The High temperature limit hysteresis threshold is equal to (THigh_Limit - THigh_Hyst).

The default hysteresis value is 5 °C.
7:0 TLow_Hyst[7:0] R/W 0Ah TLow_Limit Hysteresis setting.

Hysteresis value is represented by a unsigned Byte with the LSB equal to 0.5°C. The Low temperature limit hysteresis threshold is equal to (TLow_Limit + TLow_Hyst).

The default hysteresis value is 5 °C.

8.6.9 Slew_Limit Register (Address = 08h) [reset = 0500h]

This register is used to configure the temperature slew rate limit of the TMP126-Q1. The limit is formatted in a 13-bit unsigned format with the LSB (Least Significant Bit) equal to 0.03125°C/s. The range of the register is 0°C to +256°C. The default value on start-up is 0140h or 10°C/s. The slew rate limit will trigger a slew rate alert on positive slew rates that are greater than the unsigned limit as enabled by the Alert_Enable register.

Return to Register Map.

Figure 8-27 Slew_Limit Register
15 14 13 12 11 10 9 8
Reserved Slew_Rate_Limit[12:6]
R-0b R/W-05h
7 6 5 4 3 2 1 0
Slew_Rate_Limit[5:0] Reserved
R/W-00h R-00b
Table 8-13 Slew_Limit Register Field Descriptions
Bit Field Type Reset Description
15 Reserved R 00b Reserved
14:2 Slew_Rate_Limit[12:0] R/W 0140h 13-bit temperature slew rate limit setting.

Temperature low limit is represented by a 13-bit unsigned word with a LSB (Least Significant Bit) equal to 0.03125°C/s. The default setting for this is 10°C/s.
1:0 Reserved R 00b Reserved

8.6.10 Unique_ID1 register (Address = 09h) [reset = xxxxh]

This register contains bits 47:32 of the Unique ID for the device. The Unique ID of the device is used for NIST traceability purposes.

Return to Register Map.

Figure 8-28 Unique_ID1 Register
15 14 13 12 11 10 9 8
Unique_ID[47:40]
R-xxh
7 6 5 4 3 2 1 0
Unique_ID[39:32]
R-xxh
Table 8-14 Unique_ID4 Register Field Descriptions
Bit Field Type Reset Description
15:0 Unique_ID[47:32] R xxxxh Bits 47:32 of the device Unique ID

8.6.11 Unique_ID2 register (Address = 0Ah) [reset = xxxxh]

This register contains bits 31:16 of the Unique ID for the device.

Return to Register Map.

Figure 8-29 Unique_ID2 Register
15 14 13 12 11 10 9 8
Unique_ID[31:24]
R-xxh
7 6 5 4 3 2 1 0
Unique_ID[23:16]
R-xxh
Table 8-15 Unique_ID2 Register Field Descriptions
Bit Field Type Reset Description
15:0 Unique_ID[31:16] R xxxxh Bits 31:16 of the device Unique ID

8.6.12 Unique_ID3 register (Address = 0Bh) [reset = xxxxh]

This register contains bits 15:0 of the Unique ID for the device.

Return to Register Map.

Figure 8-30 Unique_ID3 Register
15 14 13 12 11 10 9 8
Unique_ID[15:8]
R-xxh
7 6 5 4 3 2 1 0
Unique_ID[7:0]
R-xxh
Table 8-16 Unique_ID3 Register Field Descriptions
Bit Field Type Reset Description
15:0 Unique_ID[15:0] R xxxxh Bits 15:0 of the device Unique ID.

8.6.13 Device_ID register (Address = 0Ch) [reset = 2126h]

This register indicates the device ID and device revision.

Return to Register Map.

Figure 8-31 Device_ID Register
15 14 13 12 11 10 9 8
Rev[3:0] ID[11:8]
R-2h R-1h
7 6 5 4 3 2 1 0
ID[7:0]
R-26h
Table 8-17 Device_ID Register Field Descriptions
Bit Field Type Reset Description
15:12 Rev[3:0] R 2h Device revision indicator.
11:0 ID[11:0] R 126h Device ID indicator.