JAJSGR7C October   2014  – September 2018 TMP302-Q1

PRODUCTION DATA.  

  1. 特長
  2. アプリケーション
  3. 概要
    1.     Device Images
      1.      トリップ・スレッショルド精度
  4. 改訂履歴
  5. デバイス比較表
  6. Pin Configuration and Functions
    1.     Pin Functions
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 HYSTSET
    4. 8.4 Device Functional Modes
  9. Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Configuring the TMP302-Q1
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12デバイスおよびドキュメントのサポート
    1. 12.1 ドキュメントの更新通知を受け取る方法
    2. 12.2 コミュニティ・リソース
    3. 12.3 商標
    4. 12.4 静電気放電に関する注意事項
    5. 12.5 Glossary
  13. 13メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ(パッケージ|ピン)
サーマルパッド・メカニカル・データ
発注情報

Design Requirements

Designing with the TMP302-Q1 family of devices is simple. The TMP302-Q1 family of devices is a temperature switch commonly used to signal a microprocessor in the event of an over temperature condition. The temperature at which the TMP302-Q1 family of devices issues an active low alert is determined by the configuration of the TRIPSET0 and TRIPSET1 pins. These two pins are digital inputs and must be tied either high or low, according to Table 1. The TMP302-Q1 family of devices issues an active low alert when the temperature threshold is exceeded. The device has built-in hysteresis to avoid the device from signaling the microprocessor as soon as the temperature drops below the temperature threshold. The amount of hysteresis is determined by the HYSTSET pin. This pin is a digital input and must be tied either high or low, according to Table 2.

See Figure 10 and Figure 11 for typical circuit configurations.