JAJSNM5A December   2021  – August 2022 TMP9R00-SP

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Two-Wire Timing Requirements
      1. 6.6.1 Timing Diagrams
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Temperature Measurement Data
      2. 7.3.2 Series Resistance Cancellation
      3. 7.3.3 Differential Input Capacitance
      4. 7.3.4 Sensor Fault
      5. 7.3.5 THERM Functions
    4. 7.4 Device Functional Modes
      1. 7.4.1 Shutdown Mode (SD)
    5. 7.5 Programming
      1. 7.5.1 Serial Interface
        1. 7.5.1.1 Bus Overview
        2. 7.5.1.2 Bus Definitions
        3. 7.5.1.3 Serial Bus Address
        4. 7.5.1.4 Read and Write Operations
          1. 7.5.1.4.1 Single Register Reads
          2. 7.5.1.4.2 Block Register Reads
        5. 7.5.1.5 Timeout Function
        6. 7.5.1.6 High-Speed Mode
      2. 7.5.2 TMP9R00-SP Register Reset
      3. 7.5.3 Lock Register
    6. 7.6 Register Maps
      1. 7.6.1 Register Information
        1. 7.6.1.1  Pointer Register
        2. 7.6.1.2  Local and Remote Temperature Value Registers
        3. 7.6.1.3  Software Reset Register
        4. 7.6.1.4  THERM Status Register
        5. 7.6.1.5  THERM2 Status Register
        6. 7.6.1.6  Remote Channel Open Status Register
        7. 7.6.1.7  Configuration Register
        8. 7.6.1.8  η-Factor Correction Register
        9. 7.6.1.9  Remote Temperature Offset Register
        10. 7.6.1.10 THERM Hysteresis Register
        11. 7.6.1.11 Local and Remote THERM and THERM2 Limit Registers
        12. 7.6.1.12 Block Read - Auto Increment Pointer
        13. 7.6.1.13 Lock Register
        14. 7.6.1.14 Manufacturer and Device Identification Plus Revision Registers
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curve
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  9. 9 Device and Documentation Support
    1. 9.1 Receiving Notification of Documentation Updates
    2. 9.2 サポート・リソース
    3. 9.3 Trademarks
    4. 9.4 Electrostatic Discharge Caution
    5. 9.5 Glossary
  10. 10Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6.6 Two-Wire Timing Requirements

At –55°C to 125°C and V+ = 1.7 V to 2.0 V, unless otherwise noted. With controller and target at same V+. Values are based on statistical analysis of samples tested during initial release.
FAST-MODE HIGH-SPEED MODE UNIT
MIN MAX MIN MAX
fSCL SCL operating frequency 0.001 0.4 0.001 2.56 MHz
tBUF Bus free time between stop and start condition 1300 160 ns
tHD;STA Hold time after repeated start condition.
After this period, the first clock is generated.		 600 160 ns
tSU;STA Repeated start condition setup time 600 160 ns
tSU;STO Stop condition setup time 600 160 ns
tHD;DAT Data hold time when SDA 0 -(1) 0 130 ns
tVD;DAT Data valid time (2) 0 900 – – ns
tSU;DAT Data setup time 100 20 ns
tLOW SCL clock low period 1300 250 ns
tHIGH SCL clock high period 600 60 ns
tF – SDA Data fall time 20 ×
(V+/5.5)		 300 100 ns
tF, tR – SCL Clock fall and rise time 300 40 ns
tR Rise time for SCL ≤ 100 kHz 1000 ns
Serial bus timeout 15 20 15 20 ms
(1) The maximum tHDDAT could be 0.9 µs for Fast-Mode, and is less than the maximum tVDDAT by a transition time.
(2) tVDDATA = time for data signal from SCL LOW to SDA output (HIGH to LOW, depending on which is worse).