JAJSFZ4E March   2009  – August 2018 TMS320C28341 , TMS320C28342 , TMS320C28343 , TMS320C28344 , TMS320C28345 , TMS320C28346

PRODUCTION DATA.  

  1. 1デバイスの概要
    1. 1.1 特長
    2. 1.2 アプリケーション
    3. 1.3 概要
    4. 1.4 機能ブロック図
  2. 2改訂履歴
  3. 3Device Comparison
    1. 3.1 Related Products
  4. 4Terminal Configuration and Functions
    1. 4.1 Pin Diagrams
    2. 4.2 Signal Descriptions
  5. 5Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings – Automotive
    3. 5.3 ESD Ratings – Commercial
    4. 5.4 Recommended Operating Conditions
    5. 5.5 Power Consumption Summary
      1. Table 5-1 TMS320C28346/C28344 Current Consumption by Power-Supply Pins at 300-MHz SYSCLKOUT
      2. Table 5-2 TMS320C28345/C28343 Current Consumption by Power-Supply Pins at 200-MHz SYSCLKOUT
      3. 5.5.1     Reducing Current Consumption
    6. 5.6 Electrical Characteristics
    7. 5.7 Thermal Resistance Characteristics
      1. 5.7.1 ZHH Package
      2. 5.7.2 ZFE Package
    8. 5.8 Thermal Design Considerations
    9. 5.9 Timing and Switching Characteristics
      1. 5.9.1 Timing Parameter Symbology
        1. 5.9.1.1 General Notes on Timing Parameters
        2. 5.9.1.2 Test Load Circuit
        3. 5.9.1.3 Device Clock Table
          1. Table 5-4 Clocking and Nomenclature (300-MHz Devices)
          2. Table 5-5 Clocking and Nomenclature (200-MHz Devices)
      2. 5.9.2 Power Sequencing
        1. 5.9.2.1   Power Management and Supervisory Circuit Solutions
        2. Table 5-6 Reset (XRS) Timing Requirements
      3. 5.9.3 Clock Requirements and Characteristics
        1. Table 5-7 XCLKIN/X1 Timing Requirements – PLL Enabled
        2. Table 5-8 XCLKIN/X1 Timing Requirements – PLL Disabled
        3. Table 5-9 XCLKOUT Switching Characteristics (PLL Bypassed or Enabled)
      4. 5.9.4 Peripherals
        1. 5.9.4.1 General-Purpose Input/Output (GPIO)
          1. 5.9.4.1.1 GPIO - Output Timing
            1. Table 5-10 General-Purpose Output Switching Characteristics
          2. 5.9.4.1.2 GPIO - Input Timing
            1. Table 5-11 General-Purpose Input Timing Requirements
          3. 5.9.4.1.3 Sampling Window Width for Input Signals
          4. 5.9.4.1.4 Low-Power Mode Wakeup Timing
            1. Table 5-12 IDLE Mode Timing Requirements
            2. Table 5-13 IDLE Mode Switching Characteristics
            3. Table 5-14 STANDBY Mode Timing Requirements
            4. Table 5-15 STANDBY Mode Switching Characteristics
            5. Table 5-16 HALT Mode Timing Requirements
            6. Table 5-17 HALT Mode Switching Characteristics
        2. 5.9.4.2 Enhanced Control Peripherals
          1. 5.9.4.2.1 Enhanced Pulse Width Modulator (ePWM) Timing
            1. Table 5-18 ePWM Timing Requirements
            2. Table 5-19 ePWM Switching Characteristics
          2. 5.9.4.2.2 Trip-Zone Input Timing
            1. Table 5-20 Trip-Zone Input Timing Requirements
          3. 5.9.4.2.3 High-Resolution PWM Timing
            1. Table 5-21 High-Resolution PWM Characteristics at SYSCLKOUT = (150–300 MHz)
          4. 5.9.4.2.4 Enhanced Capture (eCAP) Timing
            1. Table 5-22 Enhanced Capture (eCAP) Timing Requirements
            2. Table 5-23 eCAP Switching Characteristics
          5. 5.9.4.2.5 Enhanced Quadrature Encoder Pulse (eQEP) Timing
            1. Table 5-24 Enhanced Quadrature Encoder Pulse (eQEP) Timing Requirements
            2. Table 5-25 eQEP Switching Characteristics
          6. 5.9.4.2.6 ADC Start-of-Conversion Timing
            1. Table 5-26 External ADC Start-of-Conversion Switching Characteristics
        3. 5.9.4.3 External Interrupt Timing
          1. Table 5-27 External Interrupt Timing Requirements
          2. Table 5-28 External Interrupt Switching Characteristics
        4. 5.9.4.4 I2C Electrical Specification and Timing
          1. Table 5-29 I2C Timing
        5. 5.9.4.5 Serial Peripheral Interface (SPI) Timing
          1. 5.9.4.5.1 Master Mode Timing
            1. Table 5-30 SPI Master Mode External Timing (Clock Phase = 0)
            2. Table 5-31 SPI Master Mode External Timing (Clock Phase = 1)
          2. 5.9.4.5.2 Slave Mode Timing
            1. Table 5-32 SPI Slave Mode External Timing (Clock Phase = 0)
            2. Table 5-33 SPI Slave Mode External Timing (Clock Phase = 1)
        6. 5.9.4.6 Multichannel Buffered Serial Port (McBSP) Timing
          1. 5.9.4.6.1 McBSP Transmit and Receive Timing
            1. Table 5-34 McBSP Timing Requirements
            2. Table 5-35 McBSP Switching Characteristics
          2. 5.9.4.6.2 McBSP as SPI Master or Slave Timing
            1. Table 5-36 McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 0)
            2. Table 5-37 McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b, CLKXP = 0)
            3. Table 5-38 McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 0)
            4. Table 5-39 McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 11b, CLKXP = 0)
            5. Table 5-40 McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 1)
            6. Table 5-41 McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b, CLKXP = 1)
            7. Table 5-42 McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 1)
            8. Table 5-43 McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 11b, CLKXP = 1)
      5. 5.9.5 Emulator Connection Without Signal Buffering for the MCU
      6. 5.9.6 External Interface (XINTF) Timing
        1. 5.9.6.1 USEREADY = 0
        2. 5.9.6.2 Synchronous Mode (USEREADY = 1, READYMODE = 0)
        3. 5.9.6.3 Asynchronous Mode (USEREADY = 1, READYMODE = 1)
        4. 5.9.6.4 XINTF Signal Alignment to XCLKOUT
        5. 5.9.6.5 External Interface Read Timing
          1. Table 5-46 External Interface Read Timing Requirements
          2. Table 5-47 External Interface Read Switching Characteristics
        6. 5.9.6.6 External Interface Write Timing
          1. Table 5-48 External Interface Write Switching Characteristics
        7. 5.9.6.7 External Interface Ready-on-Read Timing With One External Wait State
          1. Table 5-49 External Interface Read Switching Characteristics (Ready-on-Read, One Wait State)
          2. Table 5-50 External Interface Read Timing Requirements (Ready-on-Read, One Wait State)
          3. Table 5-51 Synchronous XREADY Timing Requirements (Ready-on-Read, One Wait State)
          4. Table 5-52 Asynchronous XREADY Timing Requirements (Ready-on-Read, One Wait State)
        8. 5.9.6.8 External Interface Ready-on-Write Timing With One External Wait State
          1. Table 5-53 External Interface Write Switching Characteristics (Ready-on-Write, One Wait State)
          2. Table 5-54 Synchronous XREADY Timing Requirements (Ready-on-Write, One Wait State)
          3. Table 5-55 Asynchronous XREADY Timing Requirements (Ready-on-Write, One Wait State)
        9. 5.9.6.9 XHOLD and XHOLDA Timing
          1. Table 5-56 XHOLD/XHOLDA Timing Requirements
  6. 6Detailed Description
    1. 6.1 Brief Descriptions
      1. 6.1.1  C28x CPU
      2. 6.1.2  Memory Bus (Harvard Bus Architecture)
      3. 6.1.3  Peripheral Bus
      4. 6.1.4  Real-Time JTAG and Analysis
      5. 6.1.5  External Interface (XINTF)
      6. 6.1.6  M0, M1 SARAMs
      7. 6.1.7  L0, L1, L2, L3, L4, L5, L6, L7, H0, H1, H2, H3, H4, H5 SARAMs
      8. 6.1.8  Boot ROM
      9. 6.1.9  Security
      10. 6.1.10 Peripheral Interrupt Expansion (PIE) Block
      11. 6.1.11 External Interrupts (XINT1–XINT7, XNMI)
      12. 6.1.12 Oscillator and PLL
      13. 6.1.13 Watchdog
      14. 6.1.14 Peripheral Clocking
      15. 6.1.15 Low-Power Modes
      16. 6.1.16 Peripheral Frames 0, 1, 2, 3 (PFn)
      17. 6.1.17 General-Purpose Input/Output (GPIO) Multiplexer
      18. 6.1.18 32-Bit CPU-Timers (0, 1, 2)
      19. 6.1.19 Control Peripherals
      20. 6.1.20 Serial Port Peripherals
    2. 6.2 Peripherals
      1. 6.2.1  DMA Overview
      2. 6.2.2  32-Bit CPU-Timer 0, CPU-Timer 1, CPU-Timer 2
      3. 6.2.3  Enhanced PWM Modules
      4. 6.2.4  High-Resolution PWM (HRPWM)
      5. 6.2.5  Enhanced CAP Modules
      6. 6.2.6  Enhanced QEP Modules
      7. 6.2.7  External ADC Interface
      8. 6.2.8  Multichannel Buffered Serial Port (McBSP) Module
      9. 6.2.9  Enhanced Controller Area Network (eCAN) Modules (eCAN-A and eCAN-B)
      10. 6.2.10 Serial Communications Interface (SCI) Modules (SCI-A, SCI-B, SCI-C)
      11. 6.2.11 Serial Peripheral Interface (SPI) Module (SPI-A, SPI-D)
      12. 6.2.12 Inter-Integrated Circuit (I2C)
      13. 6.2.13 GPIO MUX
      14. 6.2.14 External Interface (XINTF)
    3. 6.3 Memory Maps
    4. 6.4 Register Map
      1. 6.4.1 Device Emulation Registers
    5. 6.5 Interrupts
      1. 6.5.1 External Interrupts
    6. 6.6 System Control
      1. 6.6.1 OSC and PLL Block
        1. 6.6.1.1 External Reference Oscillator Clock Option
        2. 6.6.1.2 PLL-Based Clock Module
        3. 6.6.1.3 Loss of Input Clock
      2. 6.6.2 Watchdog Block
    7. 6.7 Low-Power Modes Block
  7. 7Applications, Implementation, and Layout
    1. 7.1 TI Design or Reference Design
  8. 8デバイスおよびドキュメントのサポート
    1. 8.1 はじめに
    2. 8.2 デバイスおよび開発ツールの項目表記
    3. 8.3 ツールとソフトウェア
    4. 8.4 ドキュメントのサポート
    5. 8.5 関連リンク
    6. 8.6 Community Resources
    7. 8.7 商標
    8. 8.8 静電気放電に関する注意事項
    9. 8.9 Glossary
  9. 9メカニカル、パッケージ、および注文情報
    1. 9.1 パッケージ情報

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • ZFE|256
サーマルパッド・メカニカル・データ
発注情報

4.2 Signal Descriptions

Table 4-1 describes the signals. The GPIO function (shown in Italics) is the default at reset. The peripheral signals that are listed under them are alternate functions. Some peripheral functions may not be available in all devices. See Table 3-1 for details. Inputs are not 5-V tolerant. All XINTF pins have a drive strength of 4 mA (typical). All GPIO pins are I/O/Z, 4-mA drive typical and have an internal pullup, which can be selectively enabled or disabled on a per-pin basis. This feature only applies to the GPIO pins. The pullups on GPIO0–GPIO11 and GPIO58–GPIO63 pins are not enabled at reset. The pullups on GPIO12–GPIO57 and GPIO64–GPIO87 are enabled upon reset.

Table 4-1 Signal Descriptions

NAME ZHH
BALL #		 ZFE
BALL #		 DESCRIPTION
JTAG
TRST M7 R8 JTAG test reset with internal pulldown. TRST, when driven high, gives the scan system control of the operations of the device. If this signal is not connected or driven low, the device operates in its functional mode, and the test reset signals are ignored.
NOTE: TRST is an active high test pin and must be maintained low at all times during normal device operation. An external pulldown resistor is recommended on this pin. The value of this resistor should be based on drive strength of the debugger pods applicable to the design. A 2.2-kΩ resistor generally offers adequate protection. Because this is application-specific, TI recommends validating each target board for proper operation of the debugger and the application. (I, ↓)
TCK P9 T11 JTAG test clock. An external pullup resistor is required on this pin. A 2.2-kΩ resistor generally offers adequate protection.(I)
TMS M8 P9 JTAG test-mode select (TMS) with internal pullup. This serial control input is clocked into the TAP controller on the rising edge of TCK. (I, ↑)
TDI L6 T8 JTAG test data input (TDI) with internal pullup. TDI is clocked into the selected register (instruction or data) on a rising edge of TCK. (I, ↑)
TDO N7 P8 JTAG scan out, test data output (TDO). The contents of the selected register (instruction or data) are shifted out of TDO on the falling edge of TCK.
EMU0 N9 P10 Emulator pin 0. When TRST is driven high, this pin is used as an interrupt to or from the emulator system and is defined as input/output through the JTAG scan. This pin is also used to put the device into boundary-scan mode. With the EMU0 pin at a logic-high state and the EMU1 pin at a logic-low state, a rising edge on the TRST pin would latch the device into boundary-scan mode.
NOTE: An external pullup resistor is recommended on this pin. The value of this resistor should be based on the drive strength of the debugger pods applicable to the design. A 2.2-kΩ to 4.7-kΩ resistor is generally adequate. Because this is application-specific, TI recommends validating each each target board for proper operation of the debugger and the application.
EMU1 L9 R10 Emulator pin 1. When TRST is driven high, this pin is used as an interrupt to or from the emulator system and is defined as input/output through the JTAG scan. This pin is also used to put the device into boundary-scan mode. With the EMU0 pin at a logic-high state and the EMU1 pin at a logic-low state, a rising edge on the TRST pin would latch the device into boundary-scan mode.
NOTE: An external pullup resistor is recommended on this pin. The value of this resistor should be based on the drive strength of the debugger pods applicable to the design. A 2.2-kΩ to 4.7-kΩ resistor is generally adequate. Because this is application-specific, TI recommends validating each target board for proper operation of the debugger and the application.
Clock
XCLKOUT B14 D16 Output clock derived from SYSCLKOUT. XCLKOUT is either the same frequency, one-half the frequency, one-fourth the frequency, or one-eighth the frequency of SYSCLKOUT. This is controlled by bit 19 (BY4CLKMODE), bits 18:16 (XTIMCLK), and bit 2 (CLKMODE) in the XINTCNF2 register. At reset, XCLKOUT = SYSCLKOUT/8. The XCLKOUT signal can be turned off by setting XINTCNF2[CLKOFF] to 1. Unlike other GPIO pins, the XCLKOUT pin is not placed in high-impedance state during a reset.
XCLKIN D9 A12 External Oscillator Input. This pin is to feed a clock from an external 3.3-V oscillator. In this case, the X1 pin must be tied to VSSK. If a crystal/resonator is used (or if an external 1.8-V oscillator is used to feed clock to X1 pin), this pin must be tied to VSS. (I)
X1 C8 A7 Internal/External Oscillator Input. To use the internal oscillator, a quartz crystal may be connected across X1 and X2. The X1 pin is referenced to the 1.8-V core digital power supply. A 1.8-V external oscillator may be connected to the X1 pin. In this case, the XCLKIN pin must be connected to VSS. If a 3.3-V external oscillator is used with the XCLKIN pin, X1 must be tied to VSSK. (I)
X2 A8 A9 Internal Oscillator Output. A quartz crystal may be connected across X1 and X2. If X2 is not used it must be left unconnected. (O)
Reset
XRS P8 T10 Device Reset (in) and Watchdog Reset (out).
Device reset. XRS causes the device to terminate execution. The PC will point to the address contained at the location 0x3FFFC0. When XRS is brought to a high level, execution begins at the location pointed to by the PC. This pin is driven low by the MCU when a watchdog reset occurs. During watchdog reset, the XRS pin is driven low for the watchdog reset duration of 512 OSCCLK cycles. (I/OD, ↑)
The output buffer of this pin is an open drain with an internal pullup. It is recommended that this pin be driven by an open-drain device.
XRSIO N8 T9 XRS I/O Control (I) -  This pin must be connected to the XRS pin on the target board. When XRS is low (reset), the level detected on this pin puts all output buffers on the device in high-impedance mode.
External ADC Interface Signals
EXTSOC1A N1 M2 External ADC SOC Group 1 A Output. Trigger for external ADC, this signal is logical OR of ePWM1/2/3 SOCA internal signals (O)
EXTSOC1B M3 M3 External ADC SOC Group 1 B Output. Trigger for external ADC, this signal is logical OR of ePWM1/2/3 SOCB internal signals (O)
EXTSOC2A M2 N1 External ADC SOC Group 2 A Output. Trigger for external ADC, this signal is logical OR of ePWM4/5/6 SOCA internal signals (O)
EXTSOC2B P1 N2 External ADC SOC Group 2 B Output. Trigger for external ADC, this signal is logical OR of ePWM4/5/6 SOCB internal signals (O)
EXTSOC3A N2 N3 External ADC SOC Group 3 A Output. Trigger for external ADC, this signal is logical OR of ePWM7/8/9 SOCA internal signals (O)
EXTSOC3B P2 P2 External ADC SOC Group3 B Output. Trigger for external ADC, this signal is logical OR of ePWM7/8/9 SOCB internal signals (O)
EXTADCCLK N3 R3 External ADC Clock Signal. Clock for external ADC support, derived from SYSCLK (O)
GPIO and Peripheral Signals
GPIO0
EPWM1A
-
-		 B1 D2 General-purpose input/output 0 (I/O/Z)
Enhanced PWM1 Output A and HRPWM channel (O)
-
-
GPIO1
EPWM1B
ECAP6
MFSRB 		C1 E1 General-purpose input/output 1 (I/O/Z)
Enhanced PWM1 Output B (O)
Enhanced Capture 6 input/output (I/O)
McBSP-B receive frame synch (I/O)
GPIO2
EPWM2A
-
-		 F5 E2 General-purpose input/output 2 (I/O/Z)
Enhanced PWM2 Output A and HRPWM channel (O)
-
-
GPIO3
EPWM2B
ECAP5
MCLKRB		 E4 E3 General-purpose input/output 3 (I/O/Z)
Enhanced PWM2 Output B (O)
Enhanced Capture 5 input/output (I/O)
McBSP-B receive clock (I/O)
GPIO4
EPWM3A
-
-		 E2 F1 General-purpose input/output 4 (I/O/Z)
Enhanced PWM3 output A and HRPWM channel (O)
-
-
GPIO5
EPWM3B
MFSRA
ECAP1		 E3 F2 General-purpose input/output 5 (I/O/Z)
Enhanced PWM3 output B (O)
McBSP-A receive frame synch (I/O)
Enhanced Capture input/output 1 (I/O)
GPIO6
EPWM4A
EPWMSYNCI
EPWMSYNCO		 F3 F3 General-purpose input/output 6 (I/O/Z)
Enhanced PWM4 output A and HRPWM channel (O)
External ePWM sync pulse input (I)
External ePWM sync pulse output (O)
GPIO7
EPWM4B
MCLKRA
ECAP2		 F2 G1 General-purpose input/output 7 (I/O/Z)
Enhanced PWM4 output B (O)
McBSP-A receive clock (I/O)
Enhanced capture input/output 2 (I/O)
GPIO8
EPWM5A
CANTXB
ADCSOCAO 		G4 G2 General-purpose input/output 8 (I/O/Z)
Enhanced PWM5 output A and HRPWM channel (O)
Enhanced CAN-B transmit (O)
ADC start-of-conversion A (O)
GPIO9
EPWM5B
SCITXDB
ECAP3		 G2 G3 General-purpose input/output 9 (I/O/Z)
Enhanced PWM5 output B (O)
SCI-B transmit data(O)
Enhanced capture input/output 3 (I/O)
GPIO10
EPWM6A
CANRXB
ADCSOCBO 		G3 H1 General-purpose input/output 10 (I/O/Z)
Enhanced PWM6 output A and HRPWM channel (O)
Enhanced CAN-B receive (I)
ADC start-of-conversion B (O)
GPIO11
EPWM6B
SCIRXDB
ECAP4		 H3 H2 General-purpose input/output 11 (I/O/Z)
Enhanced PWM6 output B (O)
SCI-B receive data (I)
Enhanced CAP Input/Output 4 (I/O)
GPIO12
TZ1
CANTXB
MDXB		 H2 H3 General-purpose input/output 12 (I/O/Z)
Trip Zone input 1 (I)
Enhanced CAN-B transmit (O)
McBSP-B transmit serial data (O)
GPIO13
TZ2
CANRXB
MDRB		 H4 J2 General-purpose input/output 13 (I/O/Z)
Trip Zone input 2 (I)
Enhanced CAN-B receive (I)
McBSP-B receive serial data (I)
GPIO14 H5 J3 General-purpose input/output 14 (I/O/Z)
TZ3/XHOLD Trip Zone input 3/External Hold Request. XHOLD, when active (low), requests the external interface (XINTF) to release the external bus and place all buses and strobes into a high-impedance state. To prevent this from happening when TZ3 signal goes active, disable this function by writing XINTCNF2[HOLD] = 1. If this is not done, the XINTF bus will go into high impedance anytime TZ3 goes low. On the ePWM side, TZn signals are ignored by default, unless they are enabled by the code. The XINTF will release the bus when any current access is complete and there are no pending accesses on the XINTF. (I)
SCITXDB
MCLKXB		 SCI-B Transmit (O)
McBSP-B transmit clock (I/O)
GPIO15 K2 K2 General-purpose input/output 15 (I/O/Z)
TZ4/XHOLDA  Trip Zone input 4/External Hold Acknowledge. The pin function for this option is based on the direction chosen in the GPADIR register. If the pin is configured as an input, then TZ4 function is chosen. If the pin is configured as an output, then XHOLDA function is chosen. XHOLDA is driven active (low) when the XINTF has granted an XHOLD request. All XINTF buses and strobe signals will be in a high-impedance state. XHOLDA is released when the XHOLD signal is released. External devices should only drive the external bus when XHOLDA is active (low). (I/O)
SCIRXDB
MFSXB		 SCI-B receive (I)
McBSP-B transmit frame synch (I/O)
GPIO16
SPISIMOA
CANTXB
TZ5 		K4 L1 General-purpose input/output 16 (I/O/Z)
SPI slave in, master out (I/O)
Enhanced CAN-B transmit (O)
Trip Zone input 5 (I)
GPIO17
SPISOMIA
CANRXB
TZ6 		J5 L2 General-purpose input/output 17 (I/O/Z)
SPI-A slave out, master in (I/O)
Enhanced CAN-B receive (I)
Trip zone input 6 (I)
GPIO18
SPICLKA
SCITXDB
CANRXA		 L1 M1 General-purpose input/output 18 (I/O/Z)
SPI-A clock input/output (I/O)
SCI-B transmit (O)
Enhanced CAN-A receive (I)
GPIO19
SPISTEA
SCIRXDB
CANTXA		 P3 T4 General-purpose input/output 19 (I/O/Z)
SPI-A slave transmit enable input/output (I/O)
SCI-B receive (I)
Enhanced CAN-A transmit (O)
GPIO20
EQEP1A
MDXA
CANTXB		 L4 R4 General-purpose input/output 20 (I/O/Z)
Enhanced QEP1 input A (I)
McBSP-A transmit serial data (O)
Enhanced CAN-B transmit (O)
GPIO21
EQEP1B
MDRA
CANRXB		 M4 T5 General-purpose input/output 21 (I/O/Z)
Enhanced QEP1 input B (I)
McBSP-A receive serial data (I)
Enhanced CAN-B receive (I)
GPIO22
EQEP1S
MCLKXA
SCITXDB		 N4 R5 General-purpose input/output 22 (I/O/Z)
Enhanced QEP1 strobe (I/O)
McBSP-A transmit clock (I/O)
SCI-B transmit (O)
GPIO23
EQEP1I
MFSXA
SCIRXDB		 P4 P5 General-purpose input/output 23 (I/O/Z)
Enhanced QEP1 index (I/O)
McBSP-A transmit frame synch (I/O)
SCI-B receive (I)
GPIO24
ECAP1
EQEP2A
MDXB		 P5 T6 General-purpose input/output 24 (I/O/Z)
Enhanced capture 1 (I/O)
Enhanced QEP2 input A (I)
McBSP-B transmit serial data (O)
GPIO25
ECAP2
EQEP2B
MDRB		 M5 R6 General-purpose input/output 25 (I/O/Z)
Enhanced capture 2 (I/O)
Enhanced QEP2 input B (I)
McBSP-B receive serial data (I)
GPIO26
ECAP3
EQEP2I
MCLKXB		 K6 P6 General-purpose input/output 26 (I/O/Z)
Enhanced capture 3 (I/O)
Enhanced QEP2 index (I/O)
McBSP-B transmit clock (I/O)
GPIO27
ECAP4
EQEP2S
MFSXB		 M6 T7 General-purpose input/output 27 (I/O/Z)
Enhanced capture 4 (I/O)
Enhanced QEP2 strobe (I/O)
McBSP-B transmit frame synch (I/O)
GPIO28
SCIRXDA
XZCS6 		A12 B13 General-purpose input/output 28 (I/O/Z)
SCI receive data (I)
External Interface zone 6 chip select (O)
GPIO29
SCITXDA
XA19		 C3 D1 General-purpose input/output 29. (I/O/Z)
SCI transmit data (O)
External Interface Address Line 19 (O)
GPIO30
CANRXA
XA18		 C2 C2 General-purpose input/output 30 (I/O/Z)
Enhanced CAN-A receive (I)
External Interface Address Line 18 (O)
GPIO31
CANTXA
XA17		 B2 B3 General-purpose input/output 31 (I/O/Z)
Enhanced CAN-A transmit (O)
External Interface Address Line 17 (O)
GPIO32
SDAA
EPWMSYNCI
ADCSOCAO 		P6 R7 General-purpose input/output 32 (I/O/Z)
I2C data open-drain bidirectional port (I/OD)
Enhanced PWM external sync pulse input (I)
ADC start-of-conversion A (O)
GPIO33
SCLA
EPWMSYNCO
ADCSOCBO 		N6 P7 General-purpose input/output 33 (I/O/Z)
I2C clock open-drain bidirectional port (I/OD)
Enhanced PWM external synch pulse output (O)
ADC start-of-conversion B (O)
GPIO34
ECAP1
XREADY		 A13 B14 General-purpose input/output 34 (I/O/Z)
Enhanced Capture input/output 1 (I/O)
External Interface Ready signal
GPIO35
SCITXDA
XR/W 		B13 C15 General-purpose input/output 35 (I/O/Z)
SCI-A transmit data (O)
External Interface read, not write strobe
GPIO36
SCIRXDA
XZCS0 		B12 A13 General-purpose input/output 36 (I/O/Z)
SCI-A receive data (I)
External Interface zone 0 chip select (O)
GPIO37
ECAP2
XZCS7 		D11 B12 General-purpose input/output 37 (I/O/Z)
Enhanced Capture input/output 2 (I/O)
External Interface zone 7 chip select (O)
GPIO38
-
XWE0 		C12 E15 General-purpose input/output 38 (I/O/Z)
-
External Interface Write Enable 0 (O). XWE0 defaults back to GPIO38 upon reset, during which time it will be high-impedance.
GPIO39
-
XA16		 A2 B4 General-purpose input/output 39 (I/O/Z)
-
External Interface Address Line 16 (O)
GPIO40
-
XA0		 E10 C12 General-purpose input/output 40 (I/O/Z)
-
External Interface Address Line 0
GPIO41
-
XA1		 D10 B11 General-purpose input/output 41 (I/O/Z)
-
External Interface Address Line 1 (O)
GPIO42
-
XA2		 B10 C11 General-purpose input/output 42 (I/O/Z)
-
External Interface Address Line 2 (O)
GPIO43
-
XA3		 A10 B10 General-purpose input/output 43 (I/O/Z)
-
External Interface Address Line 3 (O)
GPIO44
-
XA4		 A9 C10 General-purpose input/output 44 (I/O/Z)
-
External Interface Address Line 4 (O)
GPIO45
-
XA5		 B9 C9 General-purpose input/output 45 (I/O/Z)
-
External Interface Address Line 5 (O)
GPIO46
-
XA6		 E7 B8 General-purpose input/output 46 (I/O/Z)
-
External Interface Address Line 6 (O)
GPIO47
-
XA7		 D6 C8 General-purpose input/output 47 (I/O/Z)
-
External Interface Address Line 7 (O)
GPIO48
ECAP5
XD31
SPISIMOD		 M10 R11 General-purpose input/output 48 (I/O/Z)
Enhanced Capture input/output 5 (I/O)
External Interface Data Line 31 (O)
SPI-D slave in, master out (I/O)
GPIO49
ECAP6
XD30
SPISOMID		 P10 P11 General-purpose input/output 49 (I/O/Z)
Enhanced Capture input/output 6 (I/O)
External Interface Data Line 30 (O)
SPI-D slave out, master in (I/O)
GPIO50
EQEP1A
XD29
SPICLKD		 N10 T12 General-purpose input/output 50 (I/O/Z)
Enhanced QEP 1input A (I)
External Interface Data Line 29 (O)
SPI-D Clock input/output (I/O)
GPIO51
EQEP1B
XD28
SPISTED 		N11 R12 General-purpose input/output 51 (I/O/Z)
Enhanced QEP 1input B (I)
External Interface Data Line 28 (O)
SPI-D slave transmit enable input/output (I/O)
GPIO52
EQEP1S
XD27		 M11 P12 General-purpose input/output 52 (I/O/Z)
Enhanced QEP 1Strobe (I/O)
External Interface Data Line 27 (O)
GPIO53
EQEP1I
XD26		 L11 T13 General-purpose input/output 53 (I/O/Z)
Enhanced QEP1 lndex (I/O)
External Interface Data Line 26 (O)
GPIO54
SPISIMOA
XD25
EQEP3A		 P12 R13 General-purpose input/output 54 (I/O/Z)
SPI-A slave in, master out (I/O)
External Interface Data Line 25 (O)
Enhanced QEP3 input A (I)
GPIO55
SPISOMIA
XD24
EQEP3B		 N12 P13 General-purpose input/output 55 (I/O/Z)
SPI-A slave out, master in (I/O)
External Interface Data Line 24 (O)
Enhanced QEP3 input B (I)
GPIO56
SPICLKA
XD23
EQEP3S		 P13 R14 General-purpose input/output 56 (I/O/Z)
SPI-A clock (I/O)
External Interface Data Line 23 (O)
Enhanced QEP3 strobe (I/O)
GPIO57
SPISTEA
XD22
EQEP3I		 N13 P15 General-purpose input/output 57 (I/O/Z)
SPI-A slave transmit enable (I/O)
External Interface Data Line 22 (O)
Enhanced QEP3 index (I/O)
GPIO58
MCLKRA
XD21
EPWM7A		 P14 N16 General-purpose input/output 58 (I/O/Z)
McBSP-A receive clock (I/O)
External Interface Data Line 21 (O)
Enhanced PWM 7 output A and HRPWM channel (O)
GPIO59
MFSRA
XD20
EPWM7B		 M13 N15 General-purpose input/output 59 (I/O/Z)
McBSP-A receive frame synch (I/O)
External Interface Data Line 20 (O)
Enhanced PWM 7 output B (O)
GPIO60
MCLKRB
XD19
EPWM8A		 M14 M16 General-purpose input/output 60 (I/O/Z)
McBSP-B receive clock (I/O)
External Interface Data Line 19 (O)
Enhanced PWM 8 output A and HRPWM channel (O)
GPIO61
MFSRB
XD18
EPWM8B		 L12 M15 General-purpose input/output 61 (I/O/Z)
McBSP-B receive frame synch (I/O)
External Interface Data Line 18 (O)
Enhanced PWM8 output B (O)
GPIO62
SCIRXDC
XD17
EPWM9A		 L13 M14 General-purpose input/output 62 (I/O/Z)
SCI-C receive data (I)
External Interface Data Line 17 (O)
Enhanced PWM9 output A and HRPWM channel (O)
GPIO63
SCITXDC
XD16
EPWM9B		 K13 L16 General-purpose input/output 63 (I/O/Z)
SCI-C transmit data (O)
External Interface Data Line 16 (O)
Enhanced PWM9 output B (O)
GPIO64
-
XD15		 K12 L15 General-purpose input/output 64 (I/O/Z)
-
External Interface Data Line 15 (O)
GPIO65
-
XD14		 K14 L14 General-purpose input/output 65 (I/O/Z)
-
External Interface Data Line 14 (O)
GPIO66
-
XD13		 J11 K15 General-purpose input/output 66 (I/O/Z)
-
External Interface Data Line 13 (O)
GPIO67
-
XD12		 J12 K14 General-purpose input/output 67 (I/O/Z)
-
External Interface Data Line 12 (O)
GPIO68
-
XD11		 J13 J15 General-purpose input/output 68 (I/O/Z)
-
External Interface Data Line 11 (O)
GPIO69
-
XD10		 H13 J14 General-purpose input/output 69 (I/O/Z)
-
External Interface Data Line 10 (O)
GPIO70
-
XD9		 H12 H16 General-purpose input/output 70 (I/O/Z)
-
External Interface Data Line 9 (O)
GPIO71
-
XD8		 G12 H15 General-purpose input/output 71 (I/O/Z)
-
External Interface Data Line 8 (O)
GPIO72
-
XD7		 G13 H14 General-purpose input/output 72 (I/O/Z)
-
External Interface Data Line 7 (O)
GPIO73
-
XD6		 F14 G16 General-purpose input/output 73 (I/O/Z)
-
External Interface Data Line 6 (O)
GPIO74
-
XD5		 F13 G15 General-purpose input/output 74 (I/O/Z)
-
External Interface Data Line 5 (O)
GPIO75
-
XD4		 F12 G14 General-purpose input/output 75 (I/O/Z)
-
External Interface Data Line 4 (O)
GPIO76
-
XD3		 E13 F16 General-purpose input/output 76 (I/O/Z)
-
External Interface Data Line 3 (O)
GPIO77
-
XD2		 E11 F15 General-purpose input/output 77 (I/O/Z)
-
External Interface Data Line 2 (O)
GPIO78
-
XD1		 F10 F14 General-purpose input/output 78 (I/O/Z)
-
External Interface Data Line 1 (O)
GPIO79
-
XD0		 C14 E16 General-purpose input/output 79 (I/O/Z)
-
External Interface Data Line 0 (O)
GPIO80
-
XA8		 E6 B7 General-purpose input/output 80 (I/O/Z)
-
External Interface Address Line 8 (O)
GPIO81
-
XA9		 C5 C7 General-purpose input/output 81 (I/O/Z)
-
External Interface Address Line 9 (O)
GPIO82
-
XA10		 A5 B6 General-purpose input/output 82 (I/O/Z)
-
External Interface Address Line 10 (O)
GPIO83
-
XA11		 B5 C6 General-purpose input/output 83 (I/O/Z)
-
External Interface Address Line 11 (O)
GPIO84
-
XA12		 D5 A5 General-purpose input/output 84 (I/O/Z)
 -
External Interface Address Line 12 (O)
GPIO85
-
XA13		 D4 B5 General-purpose input/output 85 (I/O/Z)
-
External Interface Address Line 13 (O)
GPIO86
-
XA14		 A3 C5 General-purpose input/output 86 (I/O/Z)
-
External Interface Address Line 14 (O)
GPIO87
-
XA15		 B3 A4 General-purpose input/output 87 (I/O/Z)
-
External Interface Address Line 15 (O)
XRD A14 D15 External Interface Read Enable (O). The XRD pin is high-impedance on reset. It stays that way as long as the XINTF clock is turned off (which happens on reset).
XWE1 C13 E14 External Memory Interface Write Enable for Upper 16-bits (O). The XWE1 pin is high-impedance on reset. It stays that way as long as the XINTF clock is turned off (which happens on reset).
CPU and I/O Power Pins
VDD18 E8 A6 Oscillator and PLL Power Pin (1.8 V)
VDD18 C7 A11
VSSK B8 A8 Oscillator Kelvin Reference Ground. This pin should not be connected to Vss. See Figure 6-29 through Figure 6-31 for proper application board connections.
VDD D1 C1 CPU and logic digital power pins (1.1 V/1.2 V)
VDD E1 C16
VDD G1 E6
VDD K3 E7
VDD M1 E8
VDD N5 E9
VDD P7 E10
VDD J3 E11
VDD J4 F5
VDD K9 F12
VDD L10 G5
VDD N14 G12
VDD K11 H5
VDD H11 H12
VDD H14 J5
VDD G10 J12
VDD E12 K3
VDD D12 K5
VDD C11 K12
VDD C10 L3
VDD B7 L5
VDD C6 L12
VDD E5 M6
VDD C4 M7
VDD M8
VDD M9
VDD M10
VDD M11
VDD P1
VDD P16
VDDIO D3 A3 Digital I/O power pins (3.3 V)
VDDIO F1 A14
VDDIO J1 B9
VDDIO L2 D5
VDDIO K5 D6
VDDIO K7 D8
VDDIO K8 D11
VDDIO P11 D12
VDDIO L14 E4
VDDIO J14 E13 Digital I/O power pins
VDDIO F11 F4
VDDIO D14 F13
VDDIO A11 J1
VDDIO C9 J4
VDDIO D7 J13
VDDIO B6 J16
VDDIO B4 L4
VDDIO L13
VDDIO M4
VDDIO M13
VDDIO N5
VDDIO N6
VDDIO N8
VDDIO N11
VDDIO N12
VDDIO R9
VDDIO T3
VDDIO T14
VSS D2 A1 Digital ground pins
VSS F4 A2
VSS G5 A10
VSS H1 A15
VSS J2 A16
VSS K1 B1
VSS L3 B2
VSS L5 B15
VSS L7 B16
VSS L8 C3
VSS M9 C4
VSS K10 C13
VSS M12 C14
VSS J10 D3
VSS H10 D4
VSS G14 D7
VSS G11 D9
VSS E14 D10
VSS D13 D13
VSS B11 D14
VSS E9 E5
VSS D8 E12
VSS A7 F6
VSS A6 F7
VSS A4 F8
VSS F9
VSS F10
VSS F11 Digital ground pins
VSS G4
VSS G6
VSS G7
VSS G8
VSS G9
VSS G10
VSS G11
VSS G13
VSS H4
VSS H6
VSS H7
VSS H8
VSS H9
VSS H10
VSS H11
VSS H13
VSS J6
VSS J7
VSS J8
VSS J9
VSS J10
VSS J11
VSS K1
VSS K4
VSS K6
VSS K7
VSS K8
VSS K9
VSS K10
VSS K11
VSS K13
VSS K16
VSS L6
VSS L7
VSS L8
VSS L9
VSS L10
VSS L11
VSS M5
VSS M12
VSS N4
VSS N7
VSS N9
VSS N10
VSS N13
VSS N14 Digital ground pins
VSS P3
VSS P4
VSS P14
VSS R1
VSS R2
VSS R15
VSS R16
VSS T1
VSS T2
VSS T15
VSS T16