JAJSFZ4E March   2009  – August 2018 TMS320C28341 , TMS320C28342 , TMS320C28343 , TMS320C28344 , TMS320C28345 , TMS320C28346

PRODUCTION DATA.  

  1. 1デバイスの概要
    1. 1.1 特長
    2. 1.2 アプリケーション
    3. 1.3 概要
    4. 1.4 機能ブロック図
  2. 2改訂履歴
  3. 3Device Comparison
    1. 3.1 Related Products
  4. 4Terminal Configuration and Functions
    1. 4.1 Pin Diagrams
    2. 4.2 Signal Descriptions
  5. 5Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings – Automotive
    3. 5.3 ESD Ratings – Commercial
    4. 5.4 Recommended Operating Conditions
    5. 5.5 Power Consumption Summary
      1. Table 5-1 TMS320C28346/C28344 Current Consumption by Power-Supply Pins at 300-MHz SYSCLKOUT
      2. Table 5-2 TMS320C28345/C28343 Current Consumption by Power-Supply Pins at 200-MHz SYSCLKOUT
      3. 5.5.1     Reducing Current Consumption
    6. 5.6 Electrical Characteristics
    7. 5.7 Thermal Resistance Characteristics
      1. 5.7.1 ZHH Package
      2. 5.7.2 ZFE Package
    8. 5.8 Thermal Design Considerations
    9. 5.9 Timing and Switching Characteristics
      1. 5.9.1 Timing Parameter Symbology
        1. 5.9.1.1 General Notes on Timing Parameters
        2. 5.9.1.2 Test Load Circuit
        3. 5.9.1.3 Device Clock Table
          1. Table 5-4 Clocking and Nomenclature (300-MHz Devices)
          2. Table 5-5 Clocking and Nomenclature (200-MHz Devices)
      2. 5.9.2 Power Sequencing
        1. 5.9.2.1   Power Management and Supervisory Circuit Solutions
        2. Table 5-6 Reset (XRS) Timing Requirements
      3. 5.9.3 Clock Requirements and Characteristics
        1. Table 5-7 XCLKIN/X1 Timing Requirements – PLL Enabled
        2. Table 5-8 XCLKIN/X1 Timing Requirements – PLL Disabled
        3. Table 5-9 XCLKOUT Switching Characteristics (PLL Bypassed or Enabled)
      4. 5.9.4 Peripherals
        1. 5.9.4.1 General-Purpose Input/Output (GPIO)
          1. 5.9.4.1.1 GPIO - Output Timing
            1. Table 5-10 General-Purpose Output Switching Characteristics
          2. 5.9.4.1.2 GPIO - Input Timing
            1. Table 5-11 General-Purpose Input Timing Requirements
          3. 5.9.4.1.3 Sampling Window Width for Input Signals
          4. 5.9.4.1.4 Low-Power Mode Wakeup Timing
            1. Table 5-12 IDLE Mode Timing Requirements
            2. Table 5-13 IDLE Mode Switching Characteristics
            3. Table 5-14 STANDBY Mode Timing Requirements
            4. Table 5-15 STANDBY Mode Switching Characteristics
            5. Table 5-16 HALT Mode Timing Requirements
            6. Table 5-17 HALT Mode Switching Characteristics
        2. 5.9.4.2 Enhanced Control Peripherals
          1. 5.9.4.2.1 Enhanced Pulse Width Modulator (ePWM) Timing
            1. Table 5-18 ePWM Timing Requirements
            2. Table 5-19 ePWM Switching Characteristics
          2. 5.9.4.2.2 Trip-Zone Input Timing
            1. Table 5-20 Trip-Zone Input Timing Requirements
          3. 5.9.4.2.3 High-Resolution PWM Timing
            1. Table 5-21 High-Resolution PWM Characteristics at SYSCLKOUT = (150–300 MHz)
          4. 5.9.4.2.4 Enhanced Capture (eCAP) Timing
            1. Table 5-22 Enhanced Capture (eCAP) Timing Requirements
            2. Table 5-23 eCAP Switching Characteristics
          5. 5.9.4.2.5 Enhanced Quadrature Encoder Pulse (eQEP) Timing
            1. Table 5-24 Enhanced Quadrature Encoder Pulse (eQEP) Timing Requirements
            2. Table 5-25 eQEP Switching Characteristics
          6. 5.9.4.2.6 ADC Start-of-Conversion Timing
            1. Table 5-26 External ADC Start-of-Conversion Switching Characteristics
        3. 5.9.4.3 External Interrupt Timing
          1. Table 5-27 External Interrupt Timing Requirements
          2. Table 5-28 External Interrupt Switching Characteristics
        4. 5.9.4.4 I2C Electrical Specification and Timing
          1. Table 5-29 I2C Timing
        5. 5.9.4.5 Serial Peripheral Interface (SPI) Timing
          1. 5.9.4.5.1 Master Mode Timing
            1. Table 5-30 SPI Master Mode External Timing (Clock Phase = 0)
            2. Table 5-31 SPI Master Mode External Timing (Clock Phase = 1)
          2. 5.9.4.5.2 Slave Mode Timing
            1. Table 5-32 SPI Slave Mode External Timing (Clock Phase = 0)
            2. Table 5-33 SPI Slave Mode External Timing (Clock Phase = 1)
        6. 5.9.4.6 Multichannel Buffered Serial Port (McBSP) Timing
          1. 5.9.4.6.1 McBSP Transmit and Receive Timing
            1. Table 5-34 McBSP Timing Requirements
            2. Table 5-35 McBSP Switching Characteristics
          2. 5.9.4.6.2 McBSP as SPI Master or Slave Timing
            1. Table 5-36 McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 0)
            2. Table 5-37 McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b, CLKXP = 0)
            3. Table 5-38 McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 0)
            4. Table 5-39 McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 11b, CLKXP = 0)
            5. Table 5-40 McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 1)
            6. Table 5-41 McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b, CLKXP = 1)
            7. Table 5-42 McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 1)
            8. Table 5-43 McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 11b, CLKXP = 1)
      5. 5.9.5 Emulator Connection Without Signal Buffering for the MCU
      6. 5.9.6 External Interface (XINTF) Timing
        1. 5.9.6.1 USEREADY = 0
        2. 5.9.6.2 Synchronous Mode (USEREADY = 1, READYMODE = 0)
        3. 5.9.6.3 Asynchronous Mode (USEREADY = 1, READYMODE = 1)
        4. 5.9.6.4 XINTF Signal Alignment to XCLKOUT
        5. 5.9.6.5 External Interface Read Timing
          1. Table 5-46 External Interface Read Timing Requirements
          2. Table 5-47 External Interface Read Switching Characteristics
        6. 5.9.6.6 External Interface Write Timing
          1. Table 5-48 External Interface Write Switching Characteristics
        7. 5.9.6.7 External Interface Ready-on-Read Timing With One External Wait State
          1. Table 5-49 External Interface Read Switching Characteristics (Ready-on-Read, One Wait State)
          2. Table 5-50 External Interface Read Timing Requirements (Ready-on-Read, One Wait State)
          3. Table 5-51 Synchronous XREADY Timing Requirements (Ready-on-Read, One Wait State)
          4. Table 5-52 Asynchronous XREADY Timing Requirements (Ready-on-Read, One Wait State)
        8. 5.9.6.8 External Interface Ready-on-Write Timing With One External Wait State
          1. Table 5-53 External Interface Write Switching Characteristics (Ready-on-Write, One Wait State)
          2. Table 5-54 Synchronous XREADY Timing Requirements (Ready-on-Write, One Wait State)
          3. Table 5-55 Asynchronous XREADY Timing Requirements (Ready-on-Write, One Wait State)
        9. 5.9.6.9 XHOLD and XHOLDA Timing
          1. Table 5-56 XHOLD/XHOLDA Timing Requirements
  6. 6Detailed Description
    1. 6.1 Brief Descriptions
      1. 6.1.1  C28x CPU
      2. 6.1.2  Memory Bus (Harvard Bus Architecture)
      3. 6.1.3  Peripheral Bus
      4. 6.1.4  Real-Time JTAG and Analysis
      5. 6.1.5  External Interface (XINTF)
      6. 6.1.6  M0, M1 SARAMs
      7. 6.1.7  L0, L1, L2, L3, L4, L5, L6, L7, H0, H1, H2, H3, H4, H5 SARAMs
      8. 6.1.8  Boot ROM
      9. 6.1.9  Security
      10. 6.1.10 Peripheral Interrupt Expansion (PIE) Block
      11. 6.1.11 External Interrupts (XINT1–XINT7, XNMI)
      12. 6.1.12 Oscillator and PLL
      13. 6.1.13 Watchdog
      14. 6.1.14 Peripheral Clocking
      15. 6.1.15 Low-Power Modes
      16. 6.1.16 Peripheral Frames 0, 1, 2, 3 (PFn)
      17. 6.1.17 General-Purpose Input/Output (GPIO) Multiplexer
      18. 6.1.18 32-Bit CPU-Timers (0, 1, 2)
      19. 6.1.19 Control Peripherals
      20. 6.1.20 Serial Port Peripherals
    2. 6.2 Peripherals
      1. 6.2.1  DMA Overview
      2. 6.2.2  32-Bit CPU-Timer 0, CPU-Timer 1, CPU-Timer 2
      3. 6.2.3  Enhanced PWM Modules
      4. 6.2.4  High-Resolution PWM (HRPWM)
      5. 6.2.5  Enhanced CAP Modules
      6. 6.2.6  Enhanced QEP Modules
      7. 6.2.7  External ADC Interface
      8. 6.2.8  Multichannel Buffered Serial Port (McBSP) Module
      9. 6.2.9  Enhanced Controller Area Network (eCAN) Modules (eCAN-A and eCAN-B)
      10. 6.2.10 Serial Communications Interface (SCI) Modules (SCI-A, SCI-B, SCI-C)
      11. 6.2.11 Serial Peripheral Interface (SPI) Module (SPI-A, SPI-D)
      12. 6.2.12 Inter-Integrated Circuit (I2C)
      13. 6.2.13 GPIO MUX
      14. 6.2.14 External Interface (XINTF)
    3. 6.3 Memory Maps
    4. 6.4 Register Map
      1. 6.4.1 Device Emulation Registers
    5. 6.5 Interrupts
      1. 6.5.1 External Interrupts
    6. 6.6 System Control
      1. 6.6.1 OSC and PLL Block
        1. 6.6.1.1 External Reference Oscillator Clock Option
        2. 6.6.1.2 PLL-Based Clock Module
        3. 6.6.1.3 Loss of Input Clock
      2. 6.6.2 Watchdog Block
    7. 6.7 Low-Power Modes Block
  7. 7Applications, Implementation, and Layout
    1. 7.1 TI Design or Reference Design
  8. 8デバイスおよびドキュメントのサポート
    1. 8.1 はじめに
    2. 8.2 デバイスおよび開発ツールの項目表記
    3. 8.3 ツールとソフトウェア
    4. 8.4 ドキュメントのサポート
    5. 8.5 関連リンク
    6. 8.6 Community Resources
    7. 8.7 商標
    8. 8.8 静電気放電に関する注意事項
    9. 8.9 Glossary
  9. 9メカニカル、パッケージ、および注文情報
    1. 9.1 パッケージ情報

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • ZAY|179
  • ZFE|256
サーマルパッド・メカニカル・データ
発注情報

6.2.13 GPIO MUX

On the 2834x devices, the GPIO MUX can multiplex up to three independent peripheral signals on a single GPIO pin in addition to providing individual pin bit-banging I/O capability. The GPIO MUX block diagram per pin is shown in Figure 6-16. Because of the open-drain capabilities of the I2C pins, the GPIO MUX block diagram for these pins differ. See the TMS320x2834x Delfino System Control and Interrupts Reference Guide for details.

NOTE

There is a 2-SYSCLKOUT cycle delay from when the write to the GPxMUXn and GPxQSELn registers occurs to when the action is valid.
TMS320C28346 TMS320C28345 TMS320C28344 TMS320C28343 TMS320C28342 TMS320C28341 gpiomux_prs439.gif
A. x stands for the port, either A or B. For example, GPxDIR refers to either the GPADIR and GPBDIR register depending on the particular GPIO pin selected.
B. GPxDAT latch/read are accessed at the same memory location.
C. This is a generic GPIO MUX block diagram. Not all options may be applicable for all GPIO pins. See the TMS320x2834x Delfino System Control and Interrupts Reference Guide for pin-specific variations.
Figure 6-16 GPIO MUX Block Diagram

The device supports 88 GPIO pins. The GPIO control and data registers are mapped to Peripheral Frame 1 to enable 32-bit operations on the registers (along with 16-bit operations). Table 6-17 shows the GPIO register mapping.

Table 6-17 GPIO Registers

NAME ADDRESS SIZE (x16) DESCRIPTION
GPIO CONTROL REGISTERS (EALLOW PROTECTED)
GPACTRL 0x6F80 2 GPIO A Control Register (GPIO0 to 31)
GPAQSEL1 0x6F82 2 GPIO A Qualifier Select 1 Register (GPIO0 to 15)
GPAQSEL2 0x6F84 2 GPIO A Qualifier Select 2 Register (GPIO16 to 31)
GPAMUX1 0x6F86 2 GPIO A MUX 1 Register (GPIO0 to 15)
GPAMUX2 0x6F88 2 GPIO A MUX 2 Register (GPIO16 to 31)
GPADIR 0x6F8A 2 GPIO A Direction Register (GPIO0 to 31)
GPAPUD 0x6F8C 2 GPIO A Pullup Disable Register (GPIO0 to 31)
Reserved 0x6F8E – 0x6F8F 2
GPBCTRL 0x6F90 2 GPIO B Control Register (GPIO32 to 63)
GPBQSEL1 0x6F92 2 GPIO B Qualifier Select 1 Register (GPIO32 to 47)
GPBQSEL2 0x6F94 2 GPIOB Qualifier Select 2 Register (GPIO48 to 63)
GPBMUX1 0x6F96 2 GPIO B MUX 1 Register (GPIO32 to 47)
GPBMUX2 0x6F98 2 GPIO B MUX 2 Register (GPIO48 to 63)
GPBDIR 0x6F9A 2 GPIO B Direction Register (GPIO32 to 63)
GPBPUD 0x6F9C 2 GPIO B Pullup Disable Register (GPIO32 to 63)
Reserved 0x6F9E – 0x6FA5 8
GPCMUX1 0x6FA6 2 GPIO C MUX1 Register (GPIO64 to 79)
GPCMUX2 0x6FA8 2 GPIO C MUX2 Register (GPIO80 to 87)
GPCDIR 0x6FAA 2 GPIO C Direction Register (GPIO64 to 87)
GPCPUD 0x6FAC 2 GPIO C Pullup Disable Register (GPIO64 to 87)
Reserved 0x6FAE – 0x6FBF 18
GPIO DATA REGISTERS (NOT EALLOW PROTECTED)
GPADAT 0x6FC0 2 GPIO A Data Register (GPIO0 to 31)
GPASET 0x6FC2 2 GPIO A Data Set Register (GPIO0 to 31)
GPACLEAR 0x6FC4 2 GPIO A Data Clear Register (GPIO0 to 31)
GPATOGGLE 0x6FC6 2 GPIO A Data Toggle Register (GPIO0 to 31)
GPBDAT 0x6FC8 2 GPIO B Data Register (GPIO32 to 63)
GPBSET 0x6FCA 2 GPIO B Data Set Register (GPIO32 to 63)
GPBCLEAR 0x6FCC 2 GPIO B Data Clear Register (GPIO32 to 63)
GPBTOGGLE 0x6FCE 2 GPIOB Data Toggle Register (GPIO32 to 63)
GPCDAT 0x6FD0 2 GPIO C Data Register (GPIO64 to 87)
GPCSET 0x6FD2 2 GPIO C Data Set Register (GPIO64 to 87)
GPCCLEAR 0x6FD4 2 GPIO C Data Clear Register (GPIO64 to 87)
GPCTOGGLE 0x6FD6 2 GPIO C Data Toggle Register (GPIO64 to 87)
Reserved 0x6FD8 – 0x6FDF 8
GPIO INTERRUPT AND LOW-POWER MODES SELECT REGISTERS (EALLOW PROTECTED)
GPIOXINT1SEL 0x6FE0 1 XINT1 GPIO Input Select Register (GPIO0 to 31)
GPIOXINT2SEL 0x6FE1 1 XINT2 GPIO Input Select Register (GPIO0 to 31)
GPIOXNMISEL 0x6FE2 1 XNMI GPIO Input Select Register (GPIO0 to 31)
GPIOXINT3SEL 0x6FE3 1 XINT3 GPIO Input Select Register (GPIO32 to 63)
GPIOXINT4SEL 0x6FE4 1 XINT4 GPIO Input Select Register (GPIO32 to 63)
GPIOXINT5SEL 0x6FE5 1 XINT5 GPIO Input Select Register (GPIO32 to 63)
GPIOXINT6SEL 0x6FE6 1 XINT6 GPIO Input Select Register (GPIO32 to 63)
GPIOINT7SEL 0x6FE7 1 XINT7 GPIO Input Select Register (GPIO32 to 63)
GPIOLPMSEL 0x6FE8 2 LPM GPIO Select Register (GPIO0 to 31)
Reserved 0x6FEA – 0x6FFF 22

Table 6-18 GPIO-A Mux Peripheral Selection Matrix

REGISTER BITS PERIPHERAL SELECTION
GPADIR
GPADAT
GPASET
GPACLR
GPATOGGLE		 GPAMUX1
GPAQSEL1		 GPIOx
GPAMUX1 = 0,0		 PER1
GPAMUX1 = 0, 1		 PER2
GPAMUX1 = 1, 0		 PER3
GPAMUX1 = 1, 1
QUALPRD0 0 1, 0 GPIO0 (I/O) EPWM1A (O) Reserved Reserved
1 3, 2 GPIO1 (I/O) EPWM1B (O) ECAP6 (I/O) MFSRB (I/O)
2 5, 4 GPIO2 (I/O) EPWM2A (O) Reserved Reserved
3 7, 6 GPIO3 (I/O) EPWM2B (O) ECAP5 (I/O) MCLKRB (I/O)
4 9, 8 GPIO4 (I/O) EPWM3A (O) Reserved Reserved
5 11, 10 GPIO5 (I/O) EPWM3B (O) MFSRA (I/O) ECAP1 (I/O)
6 13, 12 GPIO6 (I/O) EPWM4A (O) EPWMSYNCI (I) EPWMSYNCO (O)
7 15, 14 GPIO7 (I/O) EPWM4B (O) MCLKRA (I/O) ECAP2 (I/O)
QUALPRD1 8 17, 16 GPIO8 (I/O) EPWM5A (O) CANTXB (O) ADCSOCAO (O)
9 19, 18 GPIO9 (I/O) EPWM5B (O) SCITXDB (O) ECAP3 (I/O)
10 21, 20 GPIO10 (I/O) EPWM6A (O) CANRXB (I) ADCSOCBO (O)
11 23, 22 GPIO11 (I/O) EPWM6B (O) SCIRXDB (I) ECAP4 (I/O)
12 25, 24 GPIO12 (I/O) TZ1 (I) CANTXB (O) MDXB (O)
13 27, 26 GPIO13 (I/O) TZ2 (I) CANRXB (I) MDRB (I)
14 29, 28 GPIO14 (I/O) TZ3 (I)/XHOLD (I) SCITXDB (O) MCLKXB (I/O)
15 31, 30 GPIO15 (I/O) TZ4 (I)/XHOLDA (O) SCIRXDB (I) MFSXB (I/O)
GPAMUX2
GPAQSEL2 		GPAMUX2 = 0, 0 GPAMUX2 = 0, 1 GPAMUX2 = 1, 0 GPAMUX2 = 1, 1
QUALPRD2 16 1, 0 GPIO16 (I/O) SPISIMOA (I/O) CANTXB (O) TZ5 (I)
17 3, 2 GPIO17 (I/O) SPISOMIA (I/O) CANRXB (I) TZ6 (I)
18 5, 4 GPIO18 (I/O) SPICLKA (I/O) SCITXDB (O) CANRXA (I)
19 7, 6 GPIO19 (I/O) SPISTEA (I/O) SCIRXDB (I) CANTXA (O)
20 9, 8 GPIO20 (I/O) EQEP1A (I) MDXA (O) CANTXB (O)
21 11, 10 GPIO21 (I/O) EQEP1B (I) MDRA (I) CANRXB (I)
22 13, 12 GPIO22 (I/O) EQEP1S (I/O) MCLKXA (I/O) SCITXDB (O)
23 15, 14 GPIO23 (I/O) EQEP1I (I/O) MFSXA (I/O) SCIRXDB (I)
QUALPRD3 24 17, 16 GPIO24 (I/O) ECAP1 (I/O) EQEP2A (I) MDXB (O)
25 19, 18 GPIO25 (I/O) ECAP2 (I/O) EQEP2B (I) MDRB (I)
26 21, 20 GPIO26 (I/O) ECAP3 (I/O) EQEP2I (I/O) MCLKXB (I/O)
27 23, 22 GPIO27 (I/O) ECAP4 (I/O) EQEP2S (I/O) MFSXB (I/O)
28 25, 24 GPIO28 (I/O) SCIRXDA (I) XZCS6 (O)
29 27, 26 GPIO29 (I/O) SCITXDA (O) XA19 (O)
30 29, 28 GPIO30 (I/O) CANRXA (I) XA18 (O)
31 31, 30 GPIO31 (I/O) CANTXA (O) XA17 (O)

Table 6-19 GPIO-B Mux Peripheral Selection Matrix

REGISTER BITS PERIPHERAL SELECTION
GPBDIR
GPBDAT
GPBSET
GPBCLR
GPBTOGGLE		 GPBMUX1
GPBQSEL1		 GPIOx
GPBMUX1 = 0, 0		 PER1
GPBMUX1 = 0, 1		 PER2
GPBMUX1 = 1, 0		 PER3
GPBMUX1 = 1, 1
QUALPRD0 0 1, 0 GPIO32 (I/O) SDAA (I/OC)(1) EPWMSYNCI (I) ADCSOCAO (O)
1 3, 2 GPIO33 (I/O) SCLA (I/OC)(1) EPWMSYNCO (O) ADCSOCBO (O)
2 5, 4 GPIO34 (I/O) ECAP1 (I/O) XREADY (I)
3 7, 6 GPIO35 (I/O) SCITXDA (O) XR/W (O)
4 9, 8 GPIO36 (I/O) SCIRXDA (I) XZCS0 (O)
5 11, 10 GPIO37 (I/O) ECAP2 (I/O) XZCS7 (O)
6 13, 12 GPIO38 (I/O) Reserved XWE0 (O)
7 15, 14 GPIO39 (I/O) XA16 (O)
QUALPRD1 8 17, 16 GPIO40 (I/O) XA0 (O)
9 19, 18 GPIO41 (I/O) XA1 (O)
10 21, 20 GPIO42 (I/O) XA2 (O)
11 23, 22 GPIO43 (I/O) XA3 (O)
12 25, 24 GPIO44 (I/O) XA4 (O)
13 27, 26 GPIO45 (I/O) XA5 (O)
14 29, 28 GPIO46 (I/O) XA6 (O)
15 31, 30 GPIO47 (I/O) XA7 (O)
GPBMUX2
GPBQSEL2 		GPBMUX2 = 0, 0 GPBMUX2 = 0, 1 GPBMUX2 = 1, 0 GPBMUX2 = 1, 1
QUALPRD2 16 1, 0 GPIO48 (I/O) ECAP5 (I/O) XD31 (I/O) SPISIMOD (I/O)
17 3, 2 GPIO49 (I/O) ECAP6 (I/O) XD30 (I/O) SPISOMID (I/O)
18 5, 4 GPIO50 (I/O) EQEP1A (I) XD29 (I/O) SPICLKD (I/O)
19 7, 6 GPIO51 (I/O) EQEP1B (I) XD28 (I/O) SPISTED (I/O)
20 9, 8 GPIO52 (I/O) EQEP1S (I/O) XD27 (I/O) Reserved
21 11, 10 GPIO53 (I/O) EQEP1I (I/O) XD26 (I/O) Reserved
22 13, 12 GPIO54 (I/O) SPISIMOA (I/O) XD25 (I/O) EQEP3A (I)
23 15, 14 GPIO55 (I/O) SPISOMIA (I/O) XD24 (I/O) EQEP3B (I)
QUALPRD3 24 17, 16 GPIO56 (I/O) SPICLKA (I/O) XD23 (I/O) EQEP3S (I/O)
25 19, 18 GPIO57 (I/O) SPISTEA (I/O) XD22 (I/O) EQEP3I (I/O)
26 21, 20 GPIO58 (I/O) MCLKRA (I/O) XD21 (I/O) EPWM7A (O)
27 23, 22 GPIO59 (I/O) MFSRA (I/O) XD20 (I/O) EPWM7B (O)
28 25, 24 GPIO60 (I/O) MCLKRB (I/O) XD19 (I/O) EPWM8A (O)
29 27, 26 GPIO61 (I/O) MFSRB (I/O) XD18 (I/O) EPWM8B (O)
30 29, 28 GPIO62 (I/O) SCIRXDC (I) XD17 (I/O) EPWM9A (O)
31 31, 30 GPIO63 (I/O) SCITXDC (O) XD16 (I/O) EPWM9B (O)
(1) Open drain

Table 6-20 GPIO-C Mux Peripheral Selection Matrix

REGISTER BITS PERIPHERAL SELECTION
GPCDIR
GPCDAT
GPCSET
GPCCLR
GPCTOGGLE		 GPCMUX1 GPIOx or PER1
GPCMUX1 = 0, 0 or 0, 1		 PER2 or PER3
GPCMUX1 = 1, 0 or 1, 1
no qual 0 1, 0 GPIO64 (I/O) XD15 (I/O)
1 3, 2 GPIO65 (I/O) XD14 (I/O)
2 5, 4 GPIO66 (I/O) XD13 (I/O)
3 7, 6 GPIO67 (I/O) XD12 (I/O)
4 9, 8 GPIO68 (I/O) XD11 (I/O)
5 11, 10 GPIO69 (I/O) XD10 (I/O)
6 13, 12 GPIO70 (I/O) XD9 (I/O)
7 15, 14 GPIO71 (I/O) XD8 (I/O)
no qual 8 17, 16 GPIO72 (I/O) XD7 (I/O)
9 19, 18 GPIO73 (I/O) XD6 (I/O)
10 21, 20 GPIO74 (I/O) XD5 (I/O)
11 23, 22 GPIO75 (I/O) XD4 (I/O)
12 25, 24 GPIO76 (I/O) XD3 (I/O)
13 27, 26 GPIO77 (I/O) XD2 (I/O)
14 29, 28 GPIO78 (I/O) XD1 (I/O)
15 31, 30 GPIO79 (I/O) XD0 (I/O)
GPCMUX2 GPCMUX2 = 0, 0 or 0, 1 GPCMUX2 = 1, 0 or 1, 1
no qual 16 1, 0 GPIO80 (I/O) XA8 (O)
17 3, 2 GPIO81 (I/O) XA9 (O)
18 5, 4 GPIO82 (I/O) XA10 (O)
19 7, 6 GPIO83 (I/O) XA11 (O)
20 9, 8 GPIO84 (I/O) XA12 (O)
21 11, 10 GPIO85 (I/O) XA13 (O)
22 13, 12 GPIO86 (I/O) XA14 (O)
23 15, 14 GPIO87 (I/O) XA15 (O)

The user can select the type of input qualification for each GPIO pin through the GPxQSEL1/2 registers from four choices:

  • Synchronization To SYSCLKOUT Only (GPxQSEL1/2 = 0, 0): This is the default mode of all GPIO pins at reset and it simply synchronizes the input signal to the system clock (SYSCLKOUT).
  • Qualification Using Sampling Window (GPxQSEL1/2 = 0, 1 and 1, 0): In this mode the input signal, after synchronization to the system clock (SYSCLKOUT), is qualified by a specified number of cycles before the input is allowed to change.
    • TMS320C28346 TMS320C28345 TMS320C28344 TMS320C28343 TMS320C28342 TMS320C28341 qual_samp_prs439.gifFigure 6-17 Qualification Using Sampling Window
  • The sampling period is specified by the QUALPRD bits in the GPxCTRL register and is configurable in groups of 8 signals. It specifies a multiple of SYSCLKOUT cycles for sampling the input signal. The sampling window is either 3-samples or 6-samples wide and the output is only changed when all samples are the same (all 0s or all 1s) as shown in Figure 6-17 (for 6-sample mode).
  • No Synchronization (GPxQSEL1/2 = 1,1): This mode is used for peripherals where synchronization is not required (synchronization is performed within the peripheral).

Due to the multilevel multiplexing that is required on the device, there may be cases where a peripheral input signal can be mapped to more then one GPIO pin. Also, when an input signal is not selected, the input signal will default to either a 0 or 1 state, depending on the peripheral.