JAJSFZ4E March   2009  – August 2018 TMS320C28341 , TMS320C28342 , TMS320C28343 , TMS320C28344 , TMS320C28345 , TMS320C28346

PRODUCTION DATA.  

  1. 1デバイスの概要
    1. 1.1 特長
    2. 1.2 アプリケーション
    3. 1.3 概要
    4. 1.4 機能ブロック図
  2. 2改訂履歴
  3. 3Device Comparison
    1. 3.1 Related Products
  4. 4Terminal Configuration and Functions
    1. 4.1 Pin Diagrams
    2. 4.2 Signal Descriptions
  5. 5Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings – Automotive
    3. 5.3 ESD Ratings – Commercial
    4. 5.4 Recommended Operating Conditions
    5. 5.5 Power Consumption Summary
      1. Table 5-1 TMS320C28346/C28344 Current Consumption by Power-Supply Pins at 300-MHz SYSCLKOUT
      2. Table 5-2 TMS320C28345/C28343 Current Consumption by Power-Supply Pins at 200-MHz SYSCLKOUT
      3. 5.5.1     Reducing Current Consumption
    6. 5.6 Electrical Characteristics
    7. 5.7 Thermal Resistance Characteristics
      1. 5.7.1 ZHH Package
      2. 5.7.2 ZFE Package
    8. 5.8 Thermal Design Considerations
    9. 5.9 Timing and Switching Characteristics
      1. 5.9.1 Timing Parameter Symbology
        1. 5.9.1.1 General Notes on Timing Parameters
        2. 5.9.1.2 Test Load Circuit
        3. 5.9.1.3 Device Clock Table
          1. Table 5-4 Clocking and Nomenclature (300-MHz Devices)
          2. Table 5-5 Clocking and Nomenclature (200-MHz Devices)
      2. 5.9.2 Power Sequencing
        1. 5.9.2.1   Power Management and Supervisory Circuit Solutions
        2. Table 5-6 Reset (XRS) Timing Requirements
      3. 5.9.3 Clock Requirements and Characteristics
        1. Table 5-7 XCLKIN/X1 Timing Requirements – PLL Enabled
        2. Table 5-8 XCLKIN/X1 Timing Requirements – PLL Disabled
        3. Table 5-9 XCLKOUT Switching Characteristics (PLL Bypassed or Enabled)
      4. 5.9.4 Peripherals
        1. 5.9.4.1 General-Purpose Input/Output (GPIO)
          1. 5.9.4.1.1 GPIO - Output Timing
            1. Table 5-10 General-Purpose Output Switching Characteristics
          2. 5.9.4.1.2 GPIO - Input Timing
            1. Table 5-11 General-Purpose Input Timing Requirements
          3. 5.9.4.1.3 Sampling Window Width for Input Signals
          4. 5.9.4.1.4 Low-Power Mode Wakeup Timing
            1. Table 5-12 IDLE Mode Timing Requirements
            2. Table 5-13 IDLE Mode Switching Characteristics
            3. Table 5-14 STANDBY Mode Timing Requirements
            4. Table 5-15 STANDBY Mode Switching Characteristics
            5. Table 5-16 HALT Mode Timing Requirements
            6. Table 5-17 HALT Mode Switching Characteristics
        2. 5.9.4.2 Enhanced Control Peripherals
          1. 5.9.4.2.1 Enhanced Pulse Width Modulator (ePWM) Timing
            1. Table 5-18 ePWM Timing Requirements
            2. Table 5-19 ePWM Switching Characteristics
          2. 5.9.4.2.2 Trip-Zone Input Timing
            1. Table 5-20 Trip-Zone Input Timing Requirements
          3. 5.9.4.2.3 High-Resolution PWM Timing
            1. Table 5-21 High-Resolution PWM Characteristics at SYSCLKOUT = (150–300 MHz)
          4. 5.9.4.2.4 Enhanced Capture (eCAP) Timing
            1. Table 5-22 Enhanced Capture (eCAP) Timing Requirements
            2. Table 5-23 eCAP Switching Characteristics
          5. 5.9.4.2.5 Enhanced Quadrature Encoder Pulse (eQEP) Timing
            1. Table 5-24 Enhanced Quadrature Encoder Pulse (eQEP) Timing Requirements
            2. Table 5-25 eQEP Switching Characteristics
          6. 5.9.4.2.6 ADC Start-of-Conversion Timing
            1. Table 5-26 External ADC Start-of-Conversion Switching Characteristics
        3. 5.9.4.3 External Interrupt Timing
          1. Table 5-27 External Interrupt Timing Requirements
          2. Table 5-28 External Interrupt Switching Characteristics
        4. 5.9.4.4 I2C Electrical Specification and Timing
          1. Table 5-29 I2C Timing
        5. 5.9.4.5 Serial Peripheral Interface (SPI) Timing
          1. 5.9.4.5.1 Master Mode Timing
            1. Table 5-30 SPI Master Mode External Timing (Clock Phase = 0)
            2. Table 5-31 SPI Master Mode External Timing (Clock Phase = 1)
          2. 5.9.4.5.2 Slave Mode Timing
            1. Table 5-32 SPI Slave Mode External Timing (Clock Phase = 0)
            2. Table 5-33 SPI Slave Mode External Timing (Clock Phase = 1)
        6. 5.9.4.6 Multichannel Buffered Serial Port (McBSP) Timing
          1. 5.9.4.6.1 McBSP Transmit and Receive Timing
            1. Table 5-34 McBSP Timing Requirements
            2. Table 5-35 McBSP Switching Characteristics
          2. 5.9.4.6.2 McBSP as SPI Master or Slave Timing
            1. Table 5-36 McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 0)
            2. Table 5-37 McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b, CLKXP = 0)
            3. Table 5-38 McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 0)
            4. Table 5-39 McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 11b, CLKXP = 0)
            5. Table 5-40 McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 1)
            6. Table 5-41 McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b, CLKXP = 1)
            7. Table 5-42 McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 1)
            8. Table 5-43 McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 11b, CLKXP = 1)
      5. 5.9.5 Emulator Connection Without Signal Buffering for the MCU
      6. 5.9.6 External Interface (XINTF) Timing
        1. 5.9.6.1 USEREADY = 0
        2. 5.9.6.2 Synchronous Mode (USEREADY = 1, READYMODE = 0)
        3. 5.9.6.3 Asynchronous Mode (USEREADY = 1, READYMODE = 1)
        4. 5.9.6.4 XINTF Signal Alignment to XCLKOUT
        5. 5.9.6.5 External Interface Read Timing
          1. Table 5-46 External Interface Read Timing Requirements
          2. Table 5-47 External Interface Read Switching Characteristics
        6. 5.9.6.6 External Interface Write Timing
          1. Table 5-48 External Interface Write Switching Characteristics
        7. 5.9.6.7 External Interface Ready-on-Read Timing With One External Wait State
          1. Table 5-49 External Interface Read Switching Characteristics (Ready-on-Read, One Wait State)
          2. Table 5-50 External Interface Read Timing Requirements (Ready-on-Read, One Wait State)
          3. Table 5-51 Synchronous XREADY Timing Requirements (Ready-on-Read, One Wait State)
          4. Table 5-52 Asynchronous XREADY Timing Requirements (Ready-on-Read, One Wait State)
        8. 5.9.6.8 External Interface Ready-on-Write Timing With One External Wait State
          1. Table 5-53 External Interface Write Switching Characteristics (Ready-on-Write, One Wait State)
          2. Table 5-54 Synchronous XREADY Timing Requirements (Ready-on-Write, One Wait State)
          3. Table 5-55 Asynchronous XREADY Timing Requirements (Ready-on-Write, One Wait State)
        9. 5.9.6.9 XHOLD and XHOLDA Timing
          1. Table 5-56 XHOLD/XHOLDA Timing Requirements
  6. 6Detailed Description
    1. 6.1 Brief Descriptions
      1. 6.1.1  C28x CPU
      2. 6.1.2  Memory Bus (Harvard Bus Architecture)
      3. 6.1.3  Peripheral Bus
      4. 6.1.4  Real-Time JTAG and Analysis
      5. 6.1.5  External Interface (XINTF)
      6. 6.1.6  M0, M1 SARAMs
      7. 6.1.7  L0, L1, L2, L3, L4, L5, L6, L7, H0, H1, H2, H3, H4, H5 SARAMs
      8. 6.1.8  Boot ROM
      9. 6.1.9  Security
      10. 6.1.10 Peripheral Interrupt Expansion (PIE) Block
      11. 6.1.11 External Interrupts (XINT1–XINT7, XNMI)
      12. 6.1.12 Oscillator and PLL
      13. 6.1.13 Watchdog
      14. 6.1.14 Peripheral Clocking
      15. 6.1.15 Low-Power Modes
      16. 6.1.16 Peripheral Frames 0, 1, 2, 3 (PFn)
      17. 6.1.17 General-Purpose Input/Output (GPIO) Multiplexer
      18. 6.1.18 32-Bit CPU-Timers (0, 1, 2)
      19. 6.1.19 Control Peripherals
      20. 6.1.20 Serial Port Peripherals
    2. 6.2 Peripherals
      1. 6.2.1  DMA Overview
      2. 6.2.2  32-Bit CPU-Timer 0, CPU-Timer 1, CPU-Timer 2
      3. 6.2.3  Enhanced PWM Modules
      4. 6.2.4  High-Resolution PWM (HRPWM)
      5. 6.2.5  Enhanced CAP Modules
      6. 6.2.6  Enhanced QEP Modules
      7. 6.2.7  External ADC Interface
      8. 6.2.8  Multichannel Buffered Serial Port (McBSP) Module
      9. 6.2.9  Enhanced Controller Area Network (eCAN) Modules (eCAN-A and eCAN-B)
      10. 6.2.10 Serial Communications Interface (SCI) Modules (SCI-A, SCI-B, SCI-C)
      11. 6.2.11 Serial Peripheral Interface (SPI) Module (SPI-A, SPI-D)
      12. 6.2.12 Inter-Integrated Circuit (I2C)
      13. 6.2.13 GPIO MUX
      14. 6.2.14 External Interface (XINTF)
    3. 6.3 Memory Maps
    4. 6.4 Register Map
      1. 6.4.1 Device Emulation Registers
    5. 6.5 Interrupts
      1. 6.5.1 External Interrupts
    6. 6.6 System Control
      1. 6.6.1 OSC and PLL Block
        1. 6.6.1.1 External Reference Oscillator Clock Option
        2. 6.6.1.2 PLL-Based Clock Module
        3. 6.6.1.3 Loss of Input Clock
      2. 6.6.2 Watchdog Block
    7. 6.7 Low-Power Modes Block
  7. 7Applications, Implementation, and Layout
    1. 7.1 TI Design or Reference Design
  8. 8デバイスおよびドキュメントのサポート
    1. 8.1 はじめに
    2. 8.2 デバイスおよび開発ツールの項目表記
    3. 8.3 ツールとソフトウェア
    4. 8.4 ドキュメントのサポート
    5. 8.5 関連リンク
    6. 8.6 Community Resources
    7. 8.7 商標
    8. 8.8 静電気放電に関する注意事項
    9. 8.9 Glossary
  9. 9メカニカル、パッケージ、および注文情報
    1. 9.1 パッケージ情報

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • ZFE|256
サーマルパッド・メカニカル・データ
発注情報

6.2.11 Serial Peripheral Interface (SPI) Module (SPI-A, SPI-D)

The device includes the four-pin serial peripheral interface (SPI) module. Two SPI modules (SPI-A and SPI-D) are available. The SPI is a high-speed, synchronous serial I/O port that allows a serial bit stream of programmed length (1 to 16 bits) to be shifted into and out of the device at a programmable bit-transfer rate. Normally, the SPI is used for communications between the MCU controller and external peripherals or another processor. Typical applications include external I/O or peripheral expansion through devices such as shift registers, display drivers, and ADCs. Multidevice communications are supported by the master/slave operation of the SPI.

The SPI module features include:

  • Four external pins:
    • SPISOMI: SPI slave-output/master-input pin
    • SPISIMO: SPI slave-input/master-output pin
    • SPISTE: SPI slave transmit-enable pin
    • SPICLK: SPI serial-clock pin

NOTE

All four pins can be used as GPIO if the SPI module is not used.
  • Two operational modes: master and slave

    • Baud rate: 125 different programmable rates.

    TMS320C28346 TMS320C28345 TMS320C28344 TMS320C28343 TMS320C28342 TMS320C28341 q_spibrr_prs439.gif

    NOTE

    See Section 5 for maximum I/O pin toggling speed.
  • Data word length: 1 to 16 data bits
  • Four clocking schemes (controlled by clock polarity and clock phase bits) include:
    • Falling edge without phase delay: SPICLK active-high. SPI transmits data on the falling edge of the SPICLK signal and receives data on the rising edge of the SPICLK signal.
    • Falling edge with phase delay: SPICLK active-high. SPI transmits data one half-cycle ahead of the falling edge of the SPICLK signal and receives data on the falling edge of the SPICLK signal.
    • Rising edge without phase delay: SPICLK inactive-low. SPI transmits data on the rising edge of the SPICLK signal and receives data on the falling edge of the SPICLK signal.
    • Rising edge with phase delay: SPICLK inactive-low. SPI transmits data one half-cycle ahead of the rising edge of the SPICLK signal and receives data on the rising edge of the SPICLK signal.
  • Simultaneous receive and transmit operation (transmit function can be disabled in software)
  • Transmitter and receiver operations are accomplished through either interrupt-driven or polled algorithms.
  • Nine SPI module control registers: Located in control register frame beginning at address 7040h.

    • NOTE

    All registers in this module are 16-bit registers that are connected to Peripheral Frame 2. When a register is accessed, the register data is in the lower byte (7–0), and the upper byte (15–8) is read as zeros. Writing to the upper byte has no effect.

Enhanced features:

  • 16-level transmit/receive FIFO
  • Delayed transmit control

The SPI port operation is configured and controlled by the registers listed in Table 6-14 and Table 6-15.

Table 6-14 SPI-A Registers

NAME ADDRESS SIZE (x16) DESCRIPTION(1)
SPICCR 0x7040 1 SPI-A Configuration Control Register
SPICTL 0x7041 1 SPI-A Operation Control Register
SPISTS 0x7042 1 SPI-A Status Register
SPIBRR 0x7044 1 SPI-A Baud Rate Register
SPIRXEMU 0x7046 1 SPI-A Receive Emulation Buffer Register
SPIRXBUF 0x7047 1 SPI-A Serial Input Buffer Register
SPITXBUF 0x7048 1 SPI-A Serial Output Buffer Register
SPIDAT 0x7049 1 SPI-A Serial Data Register
SPIFFTX 0x704A 1 SPI-A FIFO Transmit Register
SPIFFRX 0x704B 1 SPI-A FIFO Receive Register
SPIFFCT 0x704C 1 SPI-A FIFO Control Register
SPIPRI 0x704F 1 SPI-A Priority Control Register
(1) Registers in this table are mapped to Peripheral Frame 2. This space only allows 16-bit accesses. 32-bit accesses produce undefined results.

Table 6-15 SPI-D Registers

NAME ADDRESS SIZE (x16) DESCRIPTION(1)
SPICCR 0x7780 1 SPI-D Configuration Control Register
SPICTL 0x7781 1 SPI-D Operation Control Register
SPISTS 0x7782 1 SPI-D Status Register
SPIBRR 0x7784 1 SPI-D Baud Rate Register
SPIRXEMU 0x7786 1 SPI-D Receive Emulation Buffer Register
SPIRXBUF 0x7787 1 SPI-D Serial Input Buffer Register
SPITXBUF 0x7788 1 SPI-D Serial Output Buffer Register
SPIDAT 0x7789 1 SPI-D Serial Data Register
SPIFFTX 0x778A 1 SPI-D FIFO Transmit Register
SPIFFRX 0x778B 1 SPI-D FIFO Receive Register
SPIFFCT 0x778C 1 SPI-D FIFO Control Register
SPIPRI 0x778F 1 SPI-D Priority Control Register
(1) Registers in this table are mapped to Peripheral Frame 2. This space only allows 16-bit accesses. 32-bit accesses produce undefined results.

Figure 6-14 is a block diagram of the SPI in slave mode.

TMS320C28346 TMS320C28345 TMS320C28344 TMS320C28343 TMS320C28342 TMS320C28341 fbd_spi_prs439.gif
A. SPISTE is driven low by the master for a slave device.
Figure 6-14 SPI Module Block Diagram (Slave Mode)