JAJSFZ4E March   2009  – August 2018 TMS320C28341 , TMS320C28342 , TMS320C28343 , TMS320C28344 , TMS320C28345 , TMS320C28346

PRODUCTION DATA.  

  1. 1デバイスの概要
    1. 1.1 特長
    2. 1.2 アプリケーション
    3. 1.3 概要
    4. 1.4 機能ブロック図
  2. 2改訂履歴
  3. 3Device Comparison
    1. 3.1 Related Products
  4. 4Terminal Configuration and Functions
    1. 4.1 Pin Diagrams
    2. 4.2 Signal Descriptions
  5. 5Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings – Automotive
    3. 5.3 ESD Ratings – Commercial
    4. 5.4 Recommended Operating Conditions
    5. 5.5 Power Consumption Summary
      1. Table 5-1 TMS320C28346/C28344 Current Consumption by Power-Supply Pins at 300-MHz SYSCLKOUT
      2. Table 5-2 TMS320C28345/C28343 Current Consumption by Power-Supply Pins at 200-MHz SYSCLKOUT
      3. 5.5.1     Reducing Current Consumption
    6. 5.6 Electrical Characteristics
    7. 5.7 Thermal Resistance Characteristics
      1. 5.7.1 ZHH Package
      2. 5.7.2 ZFE Package
    8. 5.8 Thermal Design Considerations
    9. 5.9 Timing and Switching Characteristics
      1. 5.9.1 Timing Parameter Symbology
        1. 5.9.1.1 General Notes on Timing Parameters
        2. 5.9.1.2 Test Load Circuit
        3. 5.9.1.3 Device Clock Table
          1. Table 5-4 Clocking and Nomenclature (300-MHz Devices)
          2. Table 5-5 Clocking and Nomenclature (200-MHz Devices)
      2. 5.9.2 Power Sequencing
        1. 5.9.2.1   Power Management and Supervisory Circuit Solutions
        2. Table 5-6 Reset (XRS) Timing Requirements
      3. 5.9.3 Clock Requirements and Characteristics
        1. Table 5-7 XCLKIN/X1 Timing Requirements – PLL Enabled
        2. Table 5-8 XCLKIN/X1 Timing Requirements – PLL Disabled
        3. Table 5-9 XCLKOUT Switching Characteristics (PLL Bypassed or Enabled)
      4. 5.9.4 Peripherals
        1. 5.9.4.1 General-Purpose Input/Output (GPIO)
          1. 5.9.4.1.1 GPIO - Output Timing
            1. Table 5-10 General-Purpose Output Switching Characteristics
          2. 5.9.4.1.2 GPIO - Input Timing
            1. Table 5-11 General-Purpose Input Timing Requirements
          3. 5.9.4.1.3 Sampling Window Width for Input Signals
          4. 5.9.4.1.4 Low-Power Mode Wakeup Timing
            1. Table 5-12 IDLE Mode Timing Requirements
            2. Table 5-13 IDLE Mode Switching Characteristics
            3. Table 5-14 STANDBY Mode Timing Requirements
            4. Table 5-15 STANDBY Mode Switching Characteristics
            5. Table 5-16 HALT Mode Timing Requirements
            6. Table 5-17 HALT Mode Switching Characteristics
        2. 5.9.4.2 Enhanced Control Peripherals
          1. 5.9.4.2.1 Enhanced Pulse Width Modulator (ePWM) Timing
            1. Table 5-18 ePWM Timing Requirements
            2. Table 5-19 ePWM Switching Characteristics
          2. 5.9.4.2.2 Trip-Zone Input Timing
            1. Table 5-20 Trip-Zone Input Timing Requirements
          3. 5.9.4.2.3 High-Resolution PWM Timing
            1. Table 5-21 High-Resolution PWM Characteristics at SYSCLKOUT = (150–300 MHz)
          4. 5.9.4.2.4 Enhanced Capture (eCAP) Timing
            1. Table 5-22 Enhanced Capture (eCAP) Timing Requirements
            2. Table 5-23 eCAP Switching Characteristics
          5. 5.9.4.2.5 Enhanced Quadrature Encoder Pulse (eQEP) Timing
            1. Table 5-24 Enhanced Quadrature Encoder Pulse (eQEP) Timing Requirements
            2. Table 5-25 eQEP Switching Characteristics
          6. 5.9.4.2.6 ADC Start-of-Conversion Timing
            1. Table 5-26 External ADC Start-of-Conversion Switching Characteristics
        3. 5.9.4.3 External Interrupt Timing
          1. Table 5-27 External Interrupt Timing Requirements
          2. Table 5-28 External Interrupt Switching Characteristics
        4. 5.9.4.4 I2C Electrical Specification and Timing
          1. Table 5-29 I2C Timing
        5. 5.9.4.5 Serial Peripheral Interface (SPI) Timing
          1. 5.9.4.5.1 Master Mode Timing
            1. Table 5-30 SPI Master Mode External Timing (Clock Phase = 0)
            2. Table 5-31 SPI Master Mode External Timing (Clock Phase = 1)
          2. 5.9.4.5.2 Slave Mode Timing
            1. Table 5-32 SPI Slave Mode External Timing (Clock Phase = 0)
            2. Table 5-33 SPI Slave Mode External Timing (Clock Phase = 1)
        6. 5.9.4.6 Multichannel Buffered Serial Port (McBSP) Timing
          1. 5.9.4.6.1 McBSP Transmit and Receive Timing
            1. Table 5-34 McBSP Timing Requirements
            2. Table 5-35 McBSP Switching Characteristics
          2. 5.9.4.6.2 McBSP as SPI Master or Slave Timing
            1. Table 5-36 McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 0)
            2. Table 5-37 McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b, CLKXP = 0)
            3. Table 5-38 McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 0)
            4. Table 5-39 McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 11b, CLKXP = 0)
            5. Table 5-40 McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 1)
            6. Table 5-41 McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b, CLKXP = 1)
            7. Table 5-42 McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 1)
            8. Table 5-43 McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 11b, CLKXP = 1)
      5. 5.9.5 Emulator Connection Without Signal Buffering for the MCU
      6. 5.9.6 External Interface (XINTF) Timing
        1. 5.9.6.1 USEREADY = 0
        2. 5.9.6.2 Synchronous Mode (USEREADY = 1, READYMODE = 0)
        3. 5.9.6.3 Asynchronous Mode (USEREADY = 1, READYMODE = 1)
        4. 5.9.6.4 XINTF Signal Alignment to XCLKOUT
        5. 5.9.6.5 External Interface Read Timing
          1. Table 5-46 External Interface Read Timing Requirements
          2. Table 5-47 External Interface Read Switching Characteristics
        6. 5.9.6.6 External Interface Write Timing
          1. Table 5-48 External Interface Write Switching Characteristics
        7. 5.9.6.7 External Interface Ready-on-Read Timing With One External Wait State
          1. Table 5-49 External Interface Read Switching Characteristics (Ready-on-Read, One Wait State)
          2. Table 5-50 External Interface Read Timing Requirements (Ready-on-Read, One Wait State)
          3. Table 5-51 Synchronous XREADY Timing Requirements (Ready-on-Read, One Wait State)
          4. Table 5-52 Asynchronous XREADY Timing Requirements (Ready-on-Read, One Wait State)
        8. 5.9.6.8 External Interface Ready-on-Write Timing With One External Wait State
          1. Table 5-53 External Interface Write Switching Characteristics (Ready-on-Write, One Wait State)
          2. Table 5-54 Synchronous XREADY Timing Requirements (Ready-on-Write, One Wait State)
          3. Table 5-55 Asynchronous XREADY Timing Requirements (Ready-on-Write, One Wait State)
        9. 5.9.6.9 XHOLD and XHOLDA Timing
          1. Table 5-56 XHOLD/XHOLDA Timing Requirements
  6. 6Detailed Description
    1. 6.1 Brief Descriptions
      1. 6.1.1  C28x CPU
      2. 6.1.2  Memory Bus (Harvard Bus Architecture)
      3. 6.1.3  Peripheral Bus
      4. 6.1.4  Real-Time JTAG and Analysis
      5. 6.1.5  External Interface (XINTF)
      6. 6.1.6  M0, M1 SARAMs
      7. 6.1.7  L0, L1, L2, L3, L4, L5, L6, L7, H0, H1, H2, H3, H4, H5 SARAMs
      8. 6.1.8  Boot ROM
      9. 6.1.9  Security
      10. 6.1.10 Peripheral Interrupt Expansion (PIE) Block
      11. 6.1.11 External Interrupts (XINT1–XINT7, XNMI)
      12. 6.1.12 Oscillator and PLL
      13. 6.1.13 Watchdog
      14. 6.1.14 Peripheral Clocking
      15. 6.1.15 Low-Power Modes
      16. 6.1.16 Peripheral Frames 0, 1, 2, 3 (PFn)
      17. 6.1.17 General-Purpose Input/Output (GPIO) Multiplexer
      18. 6.1.18 32-Bit CPU-Timers (0, 1, 2)
      19. 6.1.19 Control Peripherals
      20. 6.1.20 Serial Port Peripherals
    2. 6.2 Peripherals
      1. 6.2.1  DMA Overview
      2. 6.2.2  32-Bit CPU-Timer 0, CPU-Timer 1, CPU-Timer 2
      3. 6.2.3  Enhanced PWM Modules
      4. 6.2.4  High-Resolution PWM (HRPWM)
      5. 6.2.5  Enhanced CAP Modules
      6. 6.2.6  Enhanced QEP Modules
      7. 6.2.7  External ADC Interface
      8. 6.2.8  Multichannel Buffered Serial Port (McBSP) Module
      9. 6.2.9  Enhanced Controller Area Network (eCAN) Modules (eCAN-A and eCAN-B)
      10. 6.2.10 Serial Communications Interface (SCI) Modules (SCI-A, SCI-B, SCI-C)
      11. 6.2.11 Serial Peripheral Interface (SPI) Module (SPI-A, SPI-D)
      12. 6.2.12 Inter-Integrated Circuit (I2C)
      13. 6.2.13 GPIO MUX
      14. 6.2.14 External Interface (XINTF)
    3. 6.3 Memory Maps
    4. 6.4 Register Map
      1. 6.4.1 Device Emulation Registers
    5. 6.5 Interrupts
      1. 6.5.1 External Interrupts
    6. 6.6 System Control
      1. 6.6.1 OSC and PLL Block
        1. 6.6.1.1 External Reference Oscillator Clock Option
        2. 6.6.1.2 PLL-Based Clock Module
        3. 6.6.1.3 Loss of Input Clock
      2. 6.6.2 Watchdog Block
    7. 6.7 Low-Power Modes Block
  7. 7Applications, Implementation, and Layout
    1. 7.1 TI Design or Reference Design
  8. 8デバイスおよびドキュメントのサポート
    1. 8.1 はじめに
    2. 8.2 デバイスおよび開発ツールの項目表記
    3. 8.3 ツールとソフトウェア
    4. 8.4 ドキュメントのサポート
    5. 8.5 関連リンク
    6. 8.6 Community Resources
    7. 8.7 商標
    8. 8.8 静電気放電に関する注意事項
    9. 8.9 Glossary
  9. 9メカニカル、パッケージ、および注文情報
    1. 9.1 パッケージ情報

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
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サーマルパッド・メカニカル・データ
発注情報

6.5 Interrupts

Figure 6-24 shows how the various interrupt sources are multiplexed.

TMS320C28346 TMS320C28345 TMS320C28344 TMS320C28343 TMS320C28342 TMS320C28341 ext_int_prs516.gif
A. DMA-accessible
Figure 6-24 External and PIE Interrupt Sources
TMS320C28346 TMS320C28345 TMS320C28344 TMS320C28343 TMS320C28342 TMS320C28341 per_int_prs439.gifFigure 6-25 External Interrupts

Eight PIE block interrupts are grouped into one CPU interrupt. In total, 12 CPU interrupt groups, with 8 interrupts per group equals 96 possible interrupts. On the C2834x devices, 64 of these are used by peripherals as shown in Table 6-28.

The TRAP #VectorNumber instruction transfers program control to the interrupt service routine corresponding to the vector specified. TRAP #0 tries to transfer program control to the address pointed to by the reset vector. The PIE vector table does not, however, include a reset vector. Therefore, TRAP #0 should not be used when the PIE is enabled. Doing so will result in undefined behavior.

When the PIE is enabled, TRAP #1 to TRAP #12 will transfer program control to the interrupt service routine corresponding to the first vector within the PIE group. For example: TRAP #1 fetches the vector from INT1.1, TRAP #2 fetches the vector from INT2.1, and so forth.

TMS320C28346 TMS320C28345 TMS320C28344 TMS320C28343 TMS320C28342 TMS320C28341 muxint_prs439.gifFigure 6-26 Multiplexing of Interrupts Using the PIE Block

Table 6-28 PIE Peripheral Interrupts(1)

CPU INTERRUPTS PIE INTERRUPTS
INTx.8 INTx.7 INTx.6 INTx.5 INTx.4 INTx.3 INTx.2 INTx.1
INT1 WAKEINT
(LPM/WD)		 TINT0
(TIMER 0)		 Reserved XINT2 XINT1 Reserved Reserved Reserved
INT2 EPWM8_TZINT
(ePWM8)		 EPWM7_TZINT
(ePWM7)		 EPWM6_TZINT
(ePWM6)		 EPWM5_TZINT
(ePWM5)		 EPWM4_TZINT
(ePWM4)		 EPWM3_TZINT
(ePWM3)		 EPWM2_TZINT
(ePWM2)		 EPWM1_TZINT
(ePWM1)
INT3 EPWM8_INT
(ePWM8)		 EPWM7_INT
(ePWM7)		 EPWM6_INT
(ePWM6)		 EPWM5_INT
(ePWM5)		 EPWM4_INT
(ePWM4)		 EPWM3_INT
(ePWM3)		 EPWM2_INT
(ePWM2)		 EPWM1_INT
(ePWM1)
INT4 Reserved Reserved ECAP6_INT
(eCAP6)		 ECAP5_INT
(eCAP5)		 ECAP4_INT
(eCAP4)		 ECAP3_INT
(eCAP3)		 ECAP2_INT
(eCAP2)		 ECAP1_INT
(eCAP1)
INT5 Reserved Reserved Reserved Reserved Reserved EQEP3_INT
(eQEP3)		 EQEP2_INT
(eQEP2)		 EQEP1_INT
(eQEP1)
INT6 SPITXINTD
(SPI-D)		 SPIRXINTD
(SPI-D)		 MXINTA
(McBSP-A)		 MRINTA
(McBSP-A)		 MXINTB
(McBSP-B)		 MRINTB
(McBSP-B)		 SPITXINTA
(SPI-A)		 SPIRXINTA
(SPI-A)
INT7 Reserved Reserved DINTCH6
(DMA)		 DINTCH5
(DMA)		 DINTCH4
(DMA)		 DINTCH3
(DMA)		 DINTCH2
(DMA)		 DINTCH1
(DMA)
INT8 Reserved Reserved SCITXINTC
(SCI-C)		 SCIRXINTC
(SCI-C)		 Reserved Reserved I2CINT2A
(I2C-A)		 I2CINT1A
(I2C-A)
INT9 ECAN1_INTB
(CAN-B)		 ECAN0_INTB
(CAN-B)		 ECAN1_INTA
(CAN-A)		 ECAN0_INTA
(CAN-A)		 SCITXINTB
(SCI-B)		 SCIRXINTB
(SCI-B)		 SCITXINTA
(SCI-A)		 SCIRXINTA
(SCI-A)
INT10 Reserved Reserved Reserved Reserved Reserved Reserved Reserved EPWM9_TZINT
(ePWM9)
INT11 Reserved Reserved Reserved Reserved Reserved Reserved Reserved EPWM9_INT
(ePWM9)
INT12 LUF
(FPU)		 LVF
(FPU)		 Reserved XINT7 XINT6 XINT5 XINT4 XINT3
(1) Out of the 96 possible interrupts, 64 interrupts are currently used. The remaining interrupts are reserved for future devices. These interrupts can be used as software interrupts if they are enabled at the PIEIFRx level, provided none of the interrupts within the group is being used by a peripheral. Otherwise, interrupts coming in from peripherals may be lost by accidentally clearing their flag while modifying the PIEIFR. To summarize, there is one safe case when the reserved interrupts could be used as software interrupts:
1) No peripheral within the group is asserting interrupts.

Table 6-29 PIE Configuration and Control Registers

NAME ADDRESS SIZE (x16) DESCRIPTION(1)
PIECTRL 0x0CE0 1 PIE, Control Register
PIEACK 0x0CE1 1 PIE, Acknowledge Register
PIEIER1 0x0CE2 1 PIE, INT1 Group Enable Register
PIEIFR1 0x0CE3 1 PIE, INT1 Group Flag Register
PIEIER2 0x0CE4 1 PIE, INT2 Group Enable Register
PIEIFR2 0x0CE5 1 PIE, INT2 Group Flag Register
PIEIER3 0x0CE6 1 PIE, INT3 Group Enable Register
PIEIFR3 0x0CE7 1 PIE, INT3 Group Flag Register
PIEIER4 0x0CE8 1 PIE, INT4 Group Enable Register
PIEIFR4 0x0CE9 1 PIE, INT4 Group Flag Register
PIEIER5 0x0CEA 1 PIE, INT5 Group Enable Register
PIEIFR5 0x0CEB 1 PIE, INT5 Group Flag Register
PIEIER6 0x0CEC 1 PIE, INT6 Group Enable Register
PIEIFR6 0x0CED 1 PIE, INT6 Group Flag Register
PIEIER7 0x0CEE 1 PIE, INT7 Group Enable Register
PIEIFR7 0x0CEF 1 PIE, INT7 Group Flag Register
PIEIER8 0x0CF0 1 PIE, INT8 Group Enable Register
PIEIFR8 0x0CF1 1 PIE, INT8 Group Flag Register
PIEIER9 0x0CF2 1 PIE, INT9 Group Enable Register
PIEIFR9 0x0CF3 1 PIE, INT9 Group Flag Register
PIEIER10 0x0CF4 1 PIE, INT10 Group Enable Register
PIEIFR10 0x0CF5 1 PIE, INT10 Group Flag Register
PIEIER11 0x0CF6 1 PIE, INT11 Group Enable Register
PIEIFR11 0x0CF7 1 PIE, INT11 Group Flag Register
PIEIER12 0x0CF8 1 PIE, INT12 Group Enable Register
PIEIFR12 0x0CF9 1 PIE, INT12 Group Flag Register
Reserved 0x0CFA – 0x0CFF 6 Reserved
(1) The PIE configuration and control registers are not protected by EALLOW mode. The PIE vector table is protected.