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This device is a member of TI's C5000™ fixed-point Digital Signal Processor (DSP) product family and is designed for low active and standby power consumption.
The device is based on the TMS320C55x DSP generation CPU processor core. The C55x DSP architecture achieves high performance and low power through increased parallelism and total focus on power savings. The CPU supports an internal bus structure that is composed of one program bus, one 32-bit data read bus and two 16-bit data read buses, two 16-bit data write buses, and additional buses dedicated to peripheral and DMA activity. These buses provide the ability to perform up to four 16-bit data reads and two 16-bit data writes in a single cycle. The device also includes four DMA controllers, each with 4 channels, providing data movement for 16 independent channel contexts without CPU intervention. Each DMA controller can perform one 32-bit data transfer per cycle, in parallel and independent of the CPU activity.
The C55x CPU provides two multiply-accumulate (MAC) units, each capable of 17-bit x 17-bit multiplication and a 32-bit add in a single cycle. A central 40-bit arithmetic and logic unit (ALU) is supported by an additional 16-bit ALU. Use of the ALUs is under instruction set control, providing the ability to optimize parallel activity and power consumption. These resources are managed in the Address Unit (AU) and Data Unit (DU) of the C55x CPU.
The C55x CPU supports a variable byte width instruction set for improved code density. The Instruction Unit (IU) performs 32-bit program fetches from internal or external memory and queues instructions for the Program Unit (PU). The PU decodes the instructions, directs tasks to the AU and DU resources, and manages the fully protected pipeline. Predictive branching capability avoids pipeline flushes on execution of conditional instructions.
The GPIO functions along with the 10-bit SAR ADC to provide sufficient pins for status, interrupts, and bit I/O for keyboards, and media interfaces.
Serial media is supported through two multimedia card and secure digital (MMC and SD) peripherals, three Inter-IC Sound (I2S Bus) modules, one serial port interface (SPI) with up to four chip selects, one master and slave multichannel serial port interface (McSPI) with up to three chip selects, one multichannel serial port (McBSP), one I2C multimaster and slave interface, and a universal asynchronous receiver/transmitter (UART) interface
The device peripheral set includes an external memory interface (EMIF) that provides glueless access to asynchronous memories, such as EPROM, NOR, NAND, and SRAM, as well as to high-speed, high-density memories such as synchronous DRAM (SDRAM) and mobile SDRAM (mSDRAM).
Additional peripherals include a configurable 16-bit universal host-port interface (UHPI), a high-speed universal serial bus (USB2.0) device mode only, a real-time clock (RTC), three general-purpose timers with one configurable as a watchdog timer, and an analog phase-locked loop (APLL) clock generator.
The device also includes a tightly coupled FFT hardware accelerate that supports 8- to 1024-point (by power of 2) real- and complex-valued FFTs and three integrated LDOs to power different sections of the device, except CVDDRTC which requires an external power source: ANA_LDO to provide 1.3 V to the SAR and power-management circuits (VDDA_ANA), DSP_LDO to provide 1.3 or 1.05 V to the DSP core (CVDD), selectable on-the-fly by software as long as operating frequency ranges are observed, and USB_LDO to provide 1.3 V to the USB core digital (USB_VDD1P3) and PHY circuits (USB_VDDA1P3).
The device is supported by the industry’s award-winning eXpressDSP™, Code Composer Studio™ Integrated Development Environment (IDE), DSP/BIOS™, Texas Instruments’ algorithm standard, and a large third-party network. Code Composer Studio IDE features code generation tools including a C Compiler and Linker, RTDX™, XDS100, XDS510™, XDS560™ emulation device drivers, and evaluation modules. The device is also supported by the C55x DSP library which features more than 50 foundational software kernels (FIR filters, IIR filters, FFTs, and various math functions) as well as chip support libraries.
PART NUMBER | PACKAGE | BODY SIZE |
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TMS320C5517AZCH20 | NFBGA (196) | 10.0 mm x 10.0 mm |
TMS320C5517AZCHA20 | NFBGA (196) | 10.0 mm x 10.0 mm |
Figure 1-1 shows the functional block diagram of the device.
This data manual revision history highlights the technical changes made from the previous revision to the device-specific data manual.
SEE | ADDITIONS, MODIFICATIONS, and DELETIONS |
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Global | Removed 225-MHz device information. |
Table 3-1 provides characteristics of the C5517 processor.
The table shows significant features of the devices, including the capacity of on-chip RAM, the peripherals, the CPU frequency, and the package type with pin count. For more detailed information on the actual device part number and maximum device operating frequency, see Section 7.1.2, Device Nomenclature.
HARDWARE FEATURES | C5517 | |||
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External Memory Interface (EMIF) | Asynchronous (8- and 16-bit bus width) SRAM, Flash (NOR, NAND), SDRAM and Mobile SDRAM (16-bit bus width)(2) |
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Peripherals Not all peripheral pins are available at the same time (for more detail, see Section 5). |
DMA | Four DMA controllers each with four channels, for a total of 16 channels |
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Timers | 2 32-Bit General-Purpose (GP) Timers 1 Additional Timer Configurable as a 32-Bit GP Timer or a Watchdog Each timer is capable of selecting its clock source among the choices of:
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UART | 1 (with RTS and CTS flow control) | |||
SPI | 1 with 4 chip selects (Master only) | |||
McSPI | 1 (Master and Slave synchronous serial bus) with 3 chip selects | |||
UHPI | 1 (A configurable 16-bit multiplexed host port interface) | |||
I2C | 1 (Master and Slave) | |||
I2S | 3 (Two Channel, Full Duplex Communication) | |||
USB 2.0 | High- and Full-Speed Device (device mode only, host mode not supported) | |||
MMC and SD | 2 MMC and SD, 256 byte read and write buffer, max 50-MHz clock for SD cards, and signaling for DMA transfers | |||
McBSP | 1 (with transmit and receive) | |||
ADC (Successive Approximation [SAR]) | 1 (10-bit, 4-input, 16-µs conversion time) | |||
Real-Time Clock (RTC) | 1 (Crystal Input, Separate Clock Domain and Power Supply) | |||
FFT Hardware Accelerator | 1 (Supports 8 to 1024-point 16-bit real and complex FFT) | |||
General-Purpose Input/Output Port (GPIO) | Up to 26 pins (with 1 Additional General-Purpose Output (XF) and 4 General-Purpose Outputs for Use With SAR) | |||
On-Chip Memory | Size and Organization |
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JTAG BSDL_ID | JTAGID Register (Value is: 0x0B95 602F) |
see Figure 6-2 | ||
CPU Frequency | MHz | 1.05-V Core | 75 MHz | |
1.3-V Core | 175 MHz | |||
1.4-V Core | 200 MHz | |||
Cycle Time | ns | 1.05-V Core | 13.3 ns | |
1.3-V Core | 5.71 ns | |||
1.4-V Core | 5 ns | |||
Voltage | Core (V) | 1.05 V (75 MHz) | ||
1.3 V (175 MHz) | ||||
1.4 V (200 MHz) | ||||
I/O (V) | 1.8 V, 2.75 V, 3.3 V | |||
LDOs | DSP_LDO | 1.3 V or 1.05 V, 250 mA max current for the digital core (to be used only to supply CVDD). Cannot be used to drive CVDD at the 1.4 V (>200 MHz) operating range. |
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ANA_LDO | 1.3 V, 4 mA max current for SAR and power management circuits (to be used only to supply VDDA_ANA) | |||
USB_LDO | 1.3 V, 25 mA max current for USB core digital and PHY circuits (to be used only to supply USB_VDD1P3 and USB_VDDA1P3) | |||
Temperature | Commercial Temperature (default) | TMS320C5517AZCH20 | ||
Industrial Temperature | TMS320C5517AZCHA20 | |||
PLL | Phase Lock Loop | 1 (Software Programmable PLL) | ||
BGA Package | 10 x 10 mm | 196-Terminal BGA (ZCH), 0.65-mm Pitch | ||
Product Status(1) | Product Preview (PP), Advance Information (AI), or Production Data (PD) |
PD |