SPRS841E March 2012 – October 2019 TMS320C6652 , TMS320C6654
PRODUCTION DATA.
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Table 6-23 provides the configuration of the EDMA3 channel controller present on the device.
DESCRIPTION | EDMA3_CC |
---|---|
Number of DMA channels in Channel Controller | 64 |
Number of QDMA channels | 8 |
Number of interrupt channels | 64 |
Number of PaRAM set entries | 512 |
Number of event queues | 4 |
Number of Transfer Controllers | 4 |
Memory Protection Existence | Yes |
Number of Memory Protection and Shadow Regions | 8 |