SPRS841E March 2012 – October 2019 TMS320C6652 , TMS320C6654
PRODUCTION DATA.
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Each transfer controller on a device is designed differently based on considerations like performance requirements, system topology (like main TeraNet bus width, external memory bus width), and so on. The parameters that determine the transfer controller configurations are:
All four parameters listed above are specified by the design of the device.
Table 6-24 provides the configuration of the EDMA3 transfer controller present on the device.
PARAMETER | EDMA3 CC | |||
---|---|---|---|---|
TC0 | TC1 | TC2 | TC3 | |
FIFOSIZE | 1024 bytes | 512 bytes | 512 bytes | 1024 bytes |
BUSWIDTH | 16 bytes | 16 bytes | 16 bytes | 16 bytes |
DSTREGDEPTH | 4 entries | 4 entries | 4 entries | 4 entries |
DBS | 64 bytes | 64 bytes | 64 bytes | 64 bytes |