SPRS841 Data sheet

SPRS841E March 2012 – October 2019 TMS320C6652 , TMS320C6654

PRODUCTION DATA.

パッケージ・オプション

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メカニカル・データ（パッケージ｜ピン）

CZH|625

サーマルパッド・メカニカル・データ

発注情報

6.2.2.1 Core-Before-IO Power Sequencing

Figure 6-1 shows the power sequencing and reset control of C6654 and C6652 for device initialization. POR may be removed after the power has been stable for the required 100 µs. RESETFULL must be held low for a period after the rising edge of POR but may be held low for longer periods if necessary. The configuration bits shared with the GPIO pins will be latched on the rising edge of RESETFULL and must meet the setup and hold times specified. SYSCLK1 must always be active before POR can be removed. Core-before-IO power sequencing is defined in Table 6-2.

NOTE

TI recommends a maximum of 100 ms between one power rail being valid, and the next power rail in the sequence starting to ramp.

TMS320C6652 TMS320C6654 Core_Before_IO_Power_Sequencing.gif

Figure 6-1 Core-Before-IO Power Sequencing

Table 6-2 Core-Before-IO Power Sequencing

TIME	SYSTEM STATE
1	Begin Power Stabilization Phase CVDD (core AVS) ramps up. POR must be held low through the power stabilization phase. Because POR is low, all the core logic that has async reset (created from POR) is put into the reset state.
2a	CVDD1 (core constant) ramps at the same time or shortly following CVDD. Although ramping CVDD1 and CVDD simultaneously is permitted, the voltage for CVDD1 must never exceed CVDD until after CVDD has reached a valid voltage. The purpose of ramping up the core supplies close to each other is to reduce crowbar current. CVDD1 should trail CVDD as this will ensure that the WLs in the memories are turned off and there is no current through the memory bit cells. If, however, CVDD1 (core constant) ramps up before CVDD (core AVS), then the worst-case current could be on the order of twice the specified draw of CVDD1.
2b	Once CVDD is valid, the clock drivers should be enabled. Although the clock inputs are not necessary at this time, they should either be driven with a valid clock or be held in a static state with one leg high and one leg low.
2c	The DDRCLK and SYSCLK1 may begin to toggle anytime between when CVDD is at a valid level and the setup time before POR goes high specified by t6.
3	Filtered versions of 1.8 V can ramp simultaneously with DVDD18. RESETSTAT is driven low once the DVDD18 supply is available. All LVCMOS input and bidirectional pins must not be driven or pulled high until DVDD18 is present. Driving an input or bidirectional pin before DVDD18 is valid could cause damage to the device.
4a	DVDD15 (1.5 V) supply is ramped up following DVDD18. Although ramping DVDD18 and DVDD15 simultaneously is permitted, the voltage for DVDD15 must never exceed DVDD18.
4b	RESET may be driven high any time after DVDD18 is at a valid level. In a POR-controlled boot, RESET must be high before POR is driven high.
5	POR must continue to remain low for at least 100 µs after power has stabilized. End Power Stabilization Phase
6	Device initialization requires 500 SYSCLK1 periods after the Power Stabilization Phase. The maximum clock period is 33.33 nsec, so a delay of an additional 16 µs is required before a rising edge of POR. The clock must be active during the entire 16 µs.
7	RESETFULL must be held low for at least 24 transitions of the SYSCLK1 after POR has stabilized at a high level.
8	The rising edge of the RESETFULL will remove the reset to the efuse farm allowing the scan to begin. Once device initialization and the efuse farm scan are complete, the RESETSTAT signal is driven high. This delay will be 10000 to 50000 clock cycles. End Device Initialization Phase
9	GPIO configuration bits must be valid for at least 12 transitions of the SYSCLK1 before the rising edge of RESETFULL
10	GPIO configuration bits must be held valid for at least 12 transitions of the SYSCLK1 after the rising edge of RESETFULL