6.7.3 EDMA3 Transfer Controller Configuration
Each transfer controller on a device is designed differently based on considerations like performance requirements, system topology (like main TeraNet bus width, external memory bus width), and so on. The parameters that determine the transfer controller configurations are:
- FIFOSIZE: Determines the size in bytes for the data FIFO that is the temporary buffer for the in-flight data. The data FIFO is where the read return data read by the TC read controller from the source endpoint is stored and subsequently written out to the destination endpoint by the TC write controller.
- BUSWIDTH: The width of the read and write data buses, in bytes, for the TC read and write controller, respectively. This is typically equal to the bus width of the main TeraNet interface.
- Default Burst Size (DBS): The DBS is the maximum number of bytes per read/write command issued by a transfer controller.
- DSTREGDEPTH: This determines the number of destination FIFO register set. The number of destination FIFO register set for a transfer controller determines the maximum number of outstanding transfer requests.
All four parameters listed above are specified by the design of the device.
Table 6-24 provides the configuration of the EDMA3 transfer controller present on the device.
Table 6-24 EDMA3 Transfer Controller Configuration
| PARAMETER |
EDMA3 CC |
| TC0 |
TC1 |
TC2 |
TC3 |
| FIFOSIZE |
1024 bytes |
512 bytes |
512 bytes |
1024 bytes |
| BUSWIDTH |
16 bytes |
16 bytes |
16 bytes |
16 bytes |
| DSTREGDEPTH |
4 entries |
4 entries |
4 entries |
4 entries |
| DBS |
64 bytes |
64 bytes |
64 bytes |
64 bytes |