SPRS814D March   2012  – October 2019 TMS320C6655 , TMS320C6657

PRODUCTION DATA.  

  1. 1 Device Overview
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Functional Block Diagram
  2. 2 Revision History
  3. 3 Device Comparison
    1. 3.1 Device Comparison
  4. 4 Terminal Configuration and Functions
    1. 4.1 Pin Diagram
    2. 4.2 Terminal Functions
  5. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Power Consumption Summary
    5. 5.5 Electrical Characteristics
    6. 5.6 Thermal Resistance Characteristics for [CZH/GZH] Package
    7. 5.7 Timing and Switching Characteristics
      1. 5.7.1  SmartReflex
        1. Table 5-1 SmartReflex 4-Pin VID Interface Switching Characteristics
      2. 5.7.2  Reset Electrical Data / Timing
        1. Table 5-2 Reset Timing Requirements
        2. Table 5-3 Reset Switching Characteristics Over Recommended Operating Conditions
        3. Table 5-4 Boot Configuration Timing Requirements
      3. 5.7.3  Main PLL Stabilization, Lock, and Reset Times
      4. 5.7.4  Main PLL Controller/SRIO/HyperLink/PCIe Clock Input Electrical Data/Timing
        1. Table 5-6 Main PLL Controller/SRIO/HyperLink/PCIe Clock Input Timing Requirements
      5. 5.7.5  DDR3 PLL Input Clock Electrical Data/Timing
        1. Table 5-7 DDR3 PLL DDRSYSCLK1(N|P) Timing Requirements
      6. 5.7.6  External Interrupts Electrical Data/Timing
        1. Table 5-8 NMI and Local Reset Timing Requirements
      7. 5.7.7  DDR3 Memory Controller Electrical Data/Timing
      8. 5.7.8  I2C Electrical Data/Timing
        1. 5.7.8.1 Inter-Integrated Circuits (I2C) Timing
          1. Table 5-9  I2C Timing Requirements
          2. Table 5-10 I2C Switching Characteristics
      9. 5.7.9  SPI Peripheral
        1. 5.7.9.1 SPI Timing
          1. Table 5-11 SPI Timing Requirements
          2. Table 5-12 SPI Switching Characteristics
      10. 5.7.10 HyperLink Electrical Data/Timing
        1. Table 5-13 HyperLink Peripheral Timing Requirements
        2. Table 5-14 HyperLink Peripheral Switching Characteristics
      11. 5.7.11 UART Peripheral
        1. Table 5-15 UART Timing Requirements
        2. Table 5-16 UART Switching Characteristics
      12. 5.7.12 EMIF16 Peripheral
        1. 5.7.12.1 EMIF16 Electrical Data/Timing
          1. Table 5-17 EMIF16 Asynchronous Memory Timing Requirements
      13. 5.7.13 MDIO Timing
        1. Table 5-18 MDIO Timing Requirements
        2. Table 5-19 MDIO Switching Characteristics
      14. 5.7.14 Timers Electrical Data/Timing
        1. Table 5-20 Timer Input Timing Requirements
        2. Table 5-21 Timer Output Switching Characteristics
      15. 5.7.15 General-Purpose Input/Output (GPIO)
        1. 5.7.15.1 GPIO Device-Specific Information
        2. 5.7.15.2 GPIO Electrical Data/Timing
          1. Table 5-22 GPIO Input Timing Requirements
          2. Table 5-23 GPIO Output Switching Characteristics
      16. 5.7.16 McBSP Electrical Data/Timing
        1. 5.7.16.1 McBSP Timing
          1. Table 5-24 McBSP Timing Requirements
          2. Table 5-25 McBSP Switching Characteristics
          3. Table 5-26 McBSP Timing Requirements for FSR When GSYNC = 1
      17. 5.7.17 uPP Timing and Switching
        1. Table 5-27 uPP Timing Requirements
        2. Table 5-28 uPP Switching Characteristics
      18. 5.7.18 Trace Electrical Data/Timing
        1. Table 5-29 DSP Trace Switching Characteristics
        2. Table 5-30 STM Trace Switching Characteristics
      19. 5.7.19 JTAG Electrical Data/Timing
        1. Table 5-31 JTAG Test Port Timing Requirements
        2. Table 5-32 JTAG Test Port Switching Characteristics
  6. 6 Detailed Description
    1. 6.1  Recommended Clock and Control Signal Transition Behavior
    2. 6.2  Power Supplies
      1. 6.2.1 Power Supply to Peripheral I/O Mapping
      2. 6.2.2 Power-Supply Sequencing
        1. 6.2.2.1 Core-Before-IO Power Sequencing
        2. 6.2.2.2 IO-Before-Core Power Sequencing
        3. 6.2.2.3 Prolonged Resets
        4. 6.2.2.4 Clocking During Power Sequencing
      3. 6.2.3 Power-Down Sequence
      4. 6.2.4 Power Supply Decoupling and Bulk Capacitors
    3. 6.3  Power Sleep Controller (PSC)
      1. 6.3.1 Power Domains
      2. 6.3.2 Clock Domains
      3. 6.3.3 PSC Register Memory Map
    4. 6.4  Reset Controller
      1. 6.4.1 Power-on Reset
      2. 6.4.2 Hard Reset
      3. 6.4.3 Soft Reset
      4. 6.4.4 Local Reset
      5. 6.4.5 Reset Priority
      6. 6.4.6 Reset Controller Register
    5. 6.5  Main PLL and PLL Controller
      1. 6.5.1 Main PLL Controller Device-Specific Information
        1. 6.5.1.1 Internal Clocks and Maximum Operating Frequencies
        2. 6.5.1.2 Main PLL Controller Operating Modes
      2. 6.5.2 PLL Controller Memory Map
        1. 6.5.2.1 PLL Secondary Control Register (SECCTL)
          1. Table 6-10 PLL Secondary Control Register (SECCTL) Field Descriptions
        2. 6.5.2.2 PLL Controller Divider Register (PLLDIV2, PLLDIV5, PLLDIV8)
          1. Table 6-11 PLL Controller Divider Register (PLLDIVn) Field Descriptions
        3. 6.5.2.3 PLL Controller Clock Align Control Register (ALNCTL)
          1. Table 6-12 PLL Controller Clock Align Control Register (ALNCTL) Field Descriptions
        4. 6.5.2.4 PLLDIV Divider Ratio Change Status Register (DCHANGE)
          1. Table 6-13 PLLDIV Divider Ratio Change Status Register (DCHANGE) Field Descriptions
        5. 6.5.2.5 SYSCLK Status Register (SYSTAT)
          1. Table 6-14 SYSCLK Status Register (SYSTAT) Field Descriptions
        6. 6.5.2.6 Reset Type Status Register (RSTYPE)
          1. Table 6-15 Reset Type Status Register (RSTYPE) Field Descriptions
        7. 6.5.2.7 Reset Control Register (RSTCTRL)
          1. Table 6-16 Reset Control Register (RSTCTRL) Field Descriptions
        8. 6.5.2.8 Reset Configuration Register (RSTCFG)
          1. Table 6-17 Reset Configuration Register (RSTCFG) Field Descriptions
        9. 6.5.2.9 Reset Isolation Register (RSISO)
          1. Table 6-18 Reset Isolation Register (RSISO) Field Descriptions
      3. 6.5.3 Main PLL Control Register
        1. Table 6-19 Main PLL Control Register 0 (MAINPLLCTL0) Field Descriptions
        2. Table 6-20 Main PLL Control Register 1 (MAINPLLCTL1) Field Descriptions
      4. 6.5.4 Main PLL and PLL Controller Initialization Sequence
    6. 6.6  DDR3 PLL
      1. 6.6.1 DDR3 PLL Control Register
        1. Table 6-21 DDR3 PLL Control Register 0 Field Descriptions
        2. Table 6-22 DDR3 PLL Control Register 1 Field Descriptions
      2. 6.6.2 DDR3 PLL Device-Specific Information
      3. 6.6.3 DDR3 PLL Initialization Sequence
    7. 6.7  Enhanced Direct Memory Access (EDMA3) Controller
      1. 6.7.1 EDMA3 Device-Specific Information
      2. 6.7.2 EDMA3 Channel Controller Configuration
      3. 6.7.3 EDMA3 Transfer Controller Configuration
      4. 6.7.4 EDMA3 Channel Synchronization Events
    8. 6.8  Interrupts
      1. 6.8.1 Interrupt Sources and Interrupt Controller
      2. 6.8.2 CIC Registers
        1. 6.8.2.1 CIC0 Register Map
        2. 6.8.2.2 CIC1 Register Map
        3. 6.8.2.3 CIC2 Register Map
      3. 6.8.3 Interprocessor Register Map
      4. 6.8.4 NMI and LRESET
    9. 6.9  Memory Protection Unit (MPU)
      1. 6.9.1 MPU Registers
        1. 6.9.1.1 MPU Register Map
        2. 6.9.1.2 Device-Specific MPU Registers
          1. 6.9.1.2.1 Configuration Register (CONFIG)
            1. Table 6-44 Configuration Register (CONFIG) Field Descriptions
      2. 6.9.2 MPU Programmable Range Registers
        1. 6.9.2.1 Programmable Range n Start Address Register (PROGn_MPSAR)
          1. Table 6-45 Programmable Range n Start Address Register (PROGn_MPSAR) Field Descriptions
        2. 6.9.2.2 Programmable Range n End Address Register (PROGn_MPEAR)
          1. Table 6-46 Programmable Range n End Address Register (PROGn_MPEAR) Field Descriptions
        3. 6.9.2.3 Programmable Range n Memory Protection Page Attribute Register (PROGn_MPPA)
          1. Table 6-47 Programmable Range n Memory Protection Page Attribute Register (PROGn_MPPA) Field Descriptions
        4. 6.9.2.4 MPU Registers Reset Values
    10. 6.10 DDR3 Memory Controller
      1. 6.10.1 DDR3 Memory Controller Device-Specific Information
    11. 6.11 I2C Peripheral
      1. 6.11.1 I2C Device-Specific Information
      2. 6.11.2 I2C Peripheral Register Description(s)
    12. 6.12 HyperLink Peripheral
      1. 6.12.1 HyperLink Device-Specific Interrupt Event
    13. 6.13 PCIe Peripheral
    14. 6.14 Ethernet Media Access Controller (EMAC)
      1. 6.14.1 EMAC Device-Specific Information
      2. 6.14.2 EMAC Peripheral Register Description(s)
      3. 6.14.3 EMAC Electrical Data/Timing (SGMII)
    15. 6.15 Management Data Input/Output (MDIO)
      1. 6.15.1 MDIO Peripheral Registers
    16. 6.16 Timers
      1. 6.16.1 Timers Device-Specific Information
    17. 6.17 Semaphore2
    18. 6.18 Multichannel Buffered Serial Port (McBSP)
      1. 6.18.1 McBSP Peripheral Register
    19. 6.19 Universal Parallel Port (uPP)
      1. 6.19.1 uPP Register Descriptions
    20. 6.20 Serial RapidIO (SRIO) Port
    21. 6.21 Turbo Decoder Coprocessor (TCP3d)
    22. 6.22 Enhanced Viterbi-Decoder Coprocessor (VCP2)
    23. 6.23 Emulation Features and Capability
      1. 6.23.1 Advanced Event Triggering (AET)
      2. 6.23.2 Trace
      3. 6.23.3 IEEE 1149.1 JTAG
        1. 6.23.3.1 IEEE 1149.1 JTAG Compatibility Statement
    24. 6.24 DSP Core Description
    25. 6.25 Memory Map Summary
    26. 6.26 Boot Sequence
    27. 6.27 Boot Modes Supported and PLL Settings
      1. 6.27.1 Boot Device Field
        1. Table 6-64 Boot Mode Pins: Boot Device Values
      2. 6.27.2 Device Configuration Field
        1. 6.27.2.1 EMIF16 / UART / No Boot Device Configuration
          1. Table 6-65 EMIF16 / UART / No Boot Configuration Field Descriptions
          2. 6.27.2.1.1 No Boot Mode
            1. Table 6-66 No Boot Configuration Field Descriptions
          3. 6.27.2.1.2 UART Boot Mode
            1. Table 6-67 UART Boot Configuration Field Descriptions
          4. 6.27.2.1.3 EMIF16 Boot Mode
            1. Table 6-68 EMIF16 Boot Configuration Field Descriptions
        2. 6.27.2.2 Serial Rapid I/O Boot Device Configuration
          1. Table 6-69 Serial Rapid I/O Configuration Field Descriptions
        3. 6.27.2.3 Ethernet (SGMII) Boot Device Configuration
          1. Table 6-70 Ethernet (SGMII) Configuration Field Descriptions
        4. 6.27.2.4 NAND Boot Device Configuration
          1. Table 6-71 NAND Configuration Field Descriptions
        5. 6.27.2.5 PCI Boot Device Configuration
          1. Table 6-72 PCI Device Configuration Field Descriptions
        6. 6.27.2.6 I2C Boot Device Configuration
          1. 6.27.2.6.1 I2C Master Mode
            1. Table 6-74 I2C Master Mode Device Configuration Field Descriptions
          2. 6.27.2.6.2 I2C Passive Mode
            1. Table 6-75 I2C Passive Mode Device Configuration Field Descriptions
        7. 6.27.2.7 SPI Boot Device Configuration
          1. Table 6-76 SPI Device Configuration Field Descriptions
        8. 6.27.2.8 HyperLink Boot Device Configuration
          1. Table 6-77 HyperLink Boot Device Configuration Field Descriptions
      3. 6.27.3 Boot Parameter Table
        1. Table 6-80 PLL Configuration Field Description
        2. 6.27.3.1   Sleep / XIP Mode Parameter Table
          1. Table 6-82 EMIF16 XIP Option Field Descriptions
        3. 6.27.3.2   SRIO Mode Boot Parameter Table
          1. Table 6-84 SRIO Boot Options Description
        4. 6.27.3.3   Ethernet Mode Boot Parameter Table
          1. Table 6-87 Ethernet Options Field Descriptions
          2. Table 6-88 SGMII Config Field Descriptions
        5. 6.27.3.4   NAND Mode Boot Parameter Table
          1. Table 6-90 NAND Boot Parameter Options Bit Field Descriptions
        6. 6.27.3.5   PCIE Mode Boot Parameter Table
          1. Table 6-92 PCIe Options Field Descriptions
        7. 6.27.3.6   I2C Mode Boot Parameter Table
          1. Table 6-94 Register Description
        8. 6.27.3.7   SPI Mode Boot Parameter Table
          1. Table 6-96 SPI Options Field Description
        9. 6.27.3.8   Hyperlink Mode Boot Parameter Table
          1. Table 6-98 Hyperlink Options Field Descriptions
        10. 6.27.3.9   UART Mode Boot Parameter Table
    28. 6.28 PLL Boot Configuration Settings
    29. 6.29 Second-Level Bootloaders
  7. 7 C66x CorePac
    1. 7.1 Memory Architecture
      1. 7.1.1 L1P Memory
      2. 7.1.2 L1D Memory
      3. 7.1.3 L2 Memory
      4. 7.1.4 MSM SRAM
      5. 7.1.5 L3 Memory
    2. 7.2 Memory Protection
    3. 7.3 Bandwidth Management
    4. 7.4 Power-Down Control
    5. 7.5 C66x CorePac Revision
      1. Table 7-2 CorePac Revision ID Register (MM_REVID) Field Descriptions
    6. 7.6 C66x CorePac Register Descriptions
  8. 8 Device Configuration
    1. 8.1 Device Configuration at Device Reset
    2. 8.2 Peripheral Selection After Device Reset
    3. 8.3 Device State Control Registers
      1. 8.3.1  Device Status Register
        1. Table 8-3 Device Status Register Field Descriptions
      2. 8.3.2  Device Configuration Register
        1. Table 8-4 Device Configuration Register Field Descriptions
      3. 8.3.3  JTAG ID (JTAGID) Register Description
        1. Table 8-5 JTAG ID Register Field Descriptions
      4. 8.3.4  Kicker Mechanism (KICK0 and KICK1) Register
      5. 8.3.5  LRESETNMI PIN Status (LRSTNMIPINSTAT) Register
        1. Table 8-6 LRESETNMI PIN Status Register (LRSTNMIPINSTAT) Field Descriptions
      6. 8.3.6  LRESETNMI PIN Status Clear (LRSTNMIPINSTAT_CLR) Register
        1. Table 8-7 LRESETNMI PIN Status Clear Register (LRSTNMIPINSTAT_CLR) Field Descriptions
      7. 8.3.7  Reset Status (RESET_STAT) Register
        1. Table 8-8 Reset Status Register (RESET_STAT) Field Descriptions
      8. 8.3.8  Reset Status Clear (RESET_STAT_CLR) Register
        1. Table 8-9 Reset Status Clear Register (RESET_STAT_CLR) Field Descriptions
      9. 8.3.9  Boot Complete (BOOTCOMPLETE) Register
        1. Table 8-10 Boot Complete Register (BOOTCOMPLETE) Field Descriptions
      10. 8.3.10 Power State Control (PWRSTATECTL) Register
        1. Table 8-11 Power State Control Register (PWRSTATECTL) Field Descriptions
      11. 8.3.11 NMI Event Generation to CorePac (NMIGRx) Register
        1. Table 8-12 NMI Generation Register (NMIGRx) Field Descriptions
      12. 8.3.12 IPC Generation (IPCGRx) Registers
        1. Table 8-13 IPC Generation Registers (IPCGRx) Field Descriptions
      13. 8.3.13 IPC Acknowledgement (IPCARx) Registers
        1. Table 8-14 IPC Acknowledgement Registers (IPCARx) Field Descriptions
      14. 8.3.14 IPC Generation Host (IPCGRH) Register
        1. Table 8-15 IPC Generation Registers (IPCGRH) Field Descriptions
      15. 8.3.15 IPC Acknowledgement Host (IPCARH) Register
        1. Table 8-16 IPC Acknowledgement Register (IPCARH) Field Descriptions
      16. 8.3.16 Timer Input Selection Register (TINPSEL)
        1. Table 8-17 Timer Input Selection Field Description (TINPSEL)
      17. 8.3.17 Timer Output Selection Register (TOUTPSEL)
        1. Table 8-18 Timer Output Selection Field Description (TOUTPSEL)
      18. 8.3.18 Reset Mux (RSTMUXx) Register
        1. Table 8-19 Reset Mux Register Field Descriptions
      19. 8.3.19 Device Speed (DEVSPEED) Register
        1. Table 8-20 Device Speed Register Field Descriptions
      20. 8.3.20 Pin Control 0 (PIN_CONTROL_0) Register
        1. Table 8-21 Pin Control 0 Register Field Descriptions
      21. 8.3.21 Pin Control 1 (PIN_CONTROL_1) Register
        1. Table 8-22 Pin Control 1 Register Field Descriptions
      22. 8.3.22 uPP Clock Source (UPP_CLOCK) Register
        1. Table 8-23 uPP Clock Source Register Field Descriptions
    4. 8.4 Pullup and Pulldown Resistors
  9. 9 System Interconnect
    1. 9.1 Internal Buses and Switch Fabrics
    2. 9.2 Switch Fabric Connections Matrix
    3. 9.3 TeraNet Switch Fabric Connections
    4. 9.4 Bus Priorities
      1. 9.4.1 Packet DMA Priority Allocation (PKTDMA_PRI_ALLOC) Register
        1. Table 9-3 Packet DMA Priority Allocation Register (PKTDMA_PRI_ALLOC) Field Descriptions
      2. 9.4.2 EMAC / uPP Priority Allocation (EMAC_UPP_PRI_ALLOC) Register
        1. Table 9-4 EMAC / uPP Priority Allocation Register (EMAC_UPP_PRI_ALLOC) Field Descriptions
  10. 10Device and Documentation Support
    1. 10.1 Device Nomenclature
    2. 10.2 Tools and Software
    3. 10.3 Documentation Support
    4. 10.4 Related Links
    5. 10.5 Support Resources
    6. 10.6 Trademarks
    7. 10.7 Electrostatic Discharge Caution
    8. 10.8 Glossary
  11. 11Mechanical Packaging and Orderable Information
    1. 11.1 Packaging Information

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • CZH|625
  • GZH|625
サーマルパッド・メカニカル・データ
発注情報

4.2 Terminal Functions

The terminal functions table (Table 4-2) identifies the external signal names, the associated pin (ball) numbers, the pin type (I, OZ, or IOZ), whether the pin has any internal pullup or pulldown resistors, and gives functional pin descriptions. Table 4-2 is arranged by function. The power terminal functions table (Table 4-3) lists the various power supply pins and ground pins and gives functional pin descriptions. Table 4-4 shows all pins arranged by signal name. Table 4-5 shows all pins arranged by ball number.

Seventy-three pins have a secondary function as well as a primary function. The secondary function is indicated with a dagger (†). One pin has a tertiary function as well as primary and secondary functions. The tertiary function is indicated with a double dagger (‡).

For more detailed information on device configuration, peripheral selection, multiplexed/shared pins, and pullup or pulldown resistors, see Section 8.4.

Use the symbol definitions in Table 4-1 when reading Table 4-2.

Table 4-1 I/O Functional Symbol Definitions

FUNCTIONAL SYMBOL DEFINITION Table 4-2
COLUMN HEADING
IPD or IPU Internal 100-µA pulldown or pullup is provided for this terminal. In most systems, a 1-kΩ resistor can be used to oppose the IPD/IPU. For more detailed information on pulldown/pullup resistors and situations in which external pulldown/pullup resistors are required, see Hardware Design Guide for KeyStone Devices. IPD/IPU
A Analog signal TYPE
GND Ground TYPE
I Input terminal TYPE
O Output terminal TYPE
S Supply voltage TYPE
Z Tri-state terminal or high impedance TYPE

Table 4-2 Terminal Functions — Signals and Control by Function

SIGNAL NAME BALL NO. TYPE IPD/IPU DESCRIPTION
Boot Configuration Pins
LENDIAN † T25 IOZ Up Endian configuration pin (Pin shared with GPIO[0])
BOOTMODE00 † R25 IOZ Down See Section 6.27 for more details

(Pins shared with GPIO[1:13])
BOOTMODE01† R23 IOZ Down
BOOTMODE02 † U25 IOZ Down
BOOTMODE03 † T23 IOZ Down
BOOTMODE04 † U24 IOZ Down
BOOTMODE05 † T22 IOZ Down
BOOTMODE06 † R21 IOZ Down
BOOTMODE07 † U22 IOZ Down
BOOTMODE08 † U23 IOZ Down
BOOTMODE09 † V23 IOZ Down
BOOTMODE10 † U21 IOZ Down
BOOTMODE11 † T21 IOZ Down
BOOTMODE12 † V22 IOZ Down
PCIESSMODE0 † W21 IOZ Down PCIe Mode selection pins (Pins shared with GPIO[14:15])
PCIESSMODE1 † V21 IOZ Down
PCIESSEN ‡ AD20 I Down PCIe module enable (Pin shared with TIMI0 and GPIO16)
Clock / Reset
CORECLKP AD18 I Core Clock Input to main PLL.
CORECLKN AE19 I
SRIOSGMIICLKP AD13 I RapidIO/SGMII Reference Clock to drive the RapidIO and SGMII SerDes
SRIOSGMIICLKN AE14 I
DDRCLKP A22 I DDR Reference Clock Input to DDR PLL
DDRCLKN B22 I
PCIECLKP AD14 I PCIe Clock Input to drive PCIe SerDes
PCIECLKN AE15 I
MCMCLKP C25 I HyperLink Reference Clock to drive the HyperLink SerDes
MCMCLKN B25 I
AVDDA1 Y15 P SYS_CLK PLL Power Supply Pin
AVDDA2 F20 P DDR_CLK PLL Power Supply Pin
SYSCLKOUT AA19 OZ Down System Clock Output to be used as a general purpose output clock for debug purposes
HOUT G2 OZ Up Interrupt output pulse created by IPCGRH
NMI H1 I Up Nonmaskable Interrupt
LRESET G4 I Up Warm Reset
LRESETNMIEN F1 I Up Enable for core selects
CORESEL0 J5 I Down Select for the target core for LRESET and NMI. For more details see Table 5-8.
CORESEL1 G5 I Down
RESETFULL J4 I Up Full Reset
RESET H4 I Up Warm Reset of non isolated portion on the IC
POR Y18 I Power-on Reset
RESETSTAT H5 O Up Reset Status Output
BOOTCOMPLETE H3 OZ Down Boot progress indication output
PTV15 F15 A PTV Compensation NMOS Reference Input. A precision resistor placed between the PTV15 pin and ground is used to closely tune the output impedance of the DDR interface drivers to 50 Ω. Presently, the recommended value for this 1% resistor is 45.3 Ω.
DDR
DDRDQM0 A8 OZ DDR EMIF Data Masks
DDRDQM1 E7 OZ
DDRDQM2 F5 OZ
DDRDQM3 E1 OZ
DDRDQM8 C12 OZ
DDRDQS0P D10 IOZ DDR EMIF Data Strobe
DDRDQS0N C10 IOZ
DDRDQS1P B7 IOZ
DDRDQS1N A7 IOZ
DDRDQS2P B4 IOZ
DDRDQS2N A4 IOZ
DDRDQS3P A2 IOZ
DDRDQS3N B2 IOZ
DDRDQS8P B13 IOZ
DDRDQS8N A13 IOZ
DDRCB00 D11 IOZ DDR EMIF Check Bits
DDRCB01 B12 IOZ
DDRCB02 C11 IOZ
DDRCB03 A12 IOZ
DDRD00 A9 IOZ DDR EMIF Data Bus
DDRD01 C9 IOZ
DDRD02 D9 IOZ
DDRD03 B9 IOZ
DDRD04 E9 IOZ
DDRD05 E10 IOZ
DDRD06 A11 IOZ
DDRD07 B11 IOZ
DDRD08 E6 IOZ
DDRD09 E8 IOZ
DDRD10 A6 IOZ
DDRD11 A5 IOZ
DDRD12 D6 IOZ
DDRD13 C7 IOZ
DDRD14 D7 IOZ
DDRD15 B8 IOZ
DDRD16 E5 IOZ
DDRD17 B3 IOZ
DDRD18 F4 IOZ
DDRD19 E4 IOZ
DDRD20 A3 IOZ
DDRD21 B5 IOZ DDR EMIF Data Bus
DDRD22 C5 IOZ
DDRD23 D5 IOZ
DDRD24 E2 IOZ
DDRD25 F2 IOZ
DDRD26 B1 IOZ
DDRD27 C1 IOZ
DDRD28 D1 IOZ
DDRD29 D3 IOZ
DDRD30 C3 IOZ DDR EMIF Data Bus
DDRD31 E3 IOZ
DDRCE0 B15 OZ DDR EMIF Chip Enables
DDRCE1 C14 OZ
DDRBA0 C18 OZ DDR EMIF Bank Address
DDRBA1 D17 OZ
DDRBA2 B19 OZ
DDRA00 D16 OZ DDR EMIF Address Bus
DDRA01 A19 OZ
DDRA02 E16 OZ
DDRA03 E15 OZ
DDRA04 B18 OZ
DDRA05 A17 OZ
DDRA06 C16 OZ
DDRA07 A18 OZ
DDRA08 D20 OZ
DDRA09 E20 OZ
DDRA10 E19 OZ
DDRA11 B20 OZ
DDRA12 D18 OZ
DDRA13 C20 OZ
DDRA14 E18 OZ
DDRA15 E17 OZ
DDRCAS D14 OZ DDR EMIF Column Address Strobe
DDRRAS A15 OZ DDR EMIF Row Address Strobe
DDRWE E13 OZ DDR EMIF Write Enable
DDRCKE0 A16 OZ DDR EMIF Clock Enable
DDRCKE1 A20 OZ DDR EMIF Clock Enable
DDRCLKOUTP0 A14 OZ DDR EMIF Output Clocks to drive SDRAMs (one clock pair per SDRAM)
DDRCLKOUTN0 B14 OZ
DDRCLKOUTP1 A21 OZ
DDRCLKOUTN1 B21 OZ
DDRODT0 E14 OZ DDR EMIF On Die Termination Outputs used to set termination on the SDRAMs
DDRODT1 D12 OZ DDR EMIF On Die Termination Outputs used to set termination on the SDRAMs
DDRRESET B16 OZ DDR Reset signal
DDRSLRATE0 C22 I Down DDR Slew rate control
DDRSLRATE1 D22 I Down
VREFSSTL E12 P Reference Voltage Input for SSTL15 buffers used by DDR EMIF (VDDS15 ÷ 2)
EMIF16
EMIFRW L5 OZ Up EMIF16 Control Signals
EMIFCE0 K5 OZ Up
EMIFCE1 G1 OZ Up
EMIFCE2 J2 OZ Up
EMIFCE3 M5 OZ Up
EMIFOE L4 OZ Up
EMIFWE K4 OZ Up
EMIFBE0 J1 OZ Up
EMIFBE1 L3 OZ Up
EMIFWAIT0 N5 I Down
EMIFWAIT1 M4 I Down EMIF16 Control Signal

This EMIF16 pin has a secondary function assigned to it as mentioned elsewhere in this table (see uPP).
EMIFA00 K1 OZ Down EMIF16 Address

These EMIF16 pins have secondary functions assigned to them as mentioned elsewhere in this table (see uPP).
EMIFA01 M3 OZ Down
EMIFA02 L2 OZ Down
EMIFA03 P5 OZ Down
EMIFA04 L1 OZ Down
EMIFA05 P4 OZ Down
EMIFA06 M2 OZ Down
EMIFA07 M1 OZ Down
EMIFA08 N2 OZ Down
EMIFA09 P3 OZ Down
EMIFA10 N1 OZ Down
EMIFA11 P2 OZ Down
EMIFA12 P1 OZ Down
EMIFA13 R5 OZ Down
EMIFA14 R3 OZ Down
EMIFA15 R4 OZ Down
EMIFA16 R2 OZ Down
EMIFA17 R1 OZ Down
EMIFA18 T4 OZ Down
EMIFA19 T1 OZ Down
EMIFA20 T5 OZ Down
EMIFA21 U1 OZ Down
EMIFA22 U2 OZ Down
EMIFA23 U3 OZ Down
EMIFD00 U4 IOZ Down EMIF16 Data

These EMIF16 pins have secondary functions assigned to them as mentioned elsewhere in this table (see uPP).
EMIFD01 U5 IOZ Down
EMIFD02 V1 IOZ Down
EMIFD03 V2 IOZ Down
EMIFD04 V3 IOZ Down
EMIFD05 V4 IOZ Down
EMIFD06 W1 IOZ Down
EMIFD07 V5 IOZ Down
EMIFD08 W2 IOZ Down
EMIFD09 Y1 IOZ Down
EMIFD10 W4 IOZ Down
EMIFD11 Y2 IOZ Down
EMIFD12 W5 IOZ Down
EMIFD13 AA1 IOZ Down
EMIFD14 AB1 IOZ Down
EMIFD15 AA2 IOZ Down
uPP
UPP_2XTXCLK † M4 I Down uPP Transmit Reference Clock (2x Transmit Rate)

This uPP pin has a primary function assigned to it as mentioned elsewhere in this table (see EMIF16).
UPP_CH0_CLK † R2 IOZ Down uPP Channel 0 Clock

This uPP pin has a primary function assigned to it as mentioned elsewhere in this table (see EMIF16).
UPP_CH0_START † R1 IOZ Down uPP Channel 0 Start

This uPP pin has a primary function assigned to it as mentioned elsewhere in this table (see EMIF16).
UPP_CH0_ENABLE † T4 IOZ Down uPP Channel 0 Enable

This uPP pin has a primary function assigned to it as mentioned elsewhere in this table (see EMIF16).
UPP_CH0_WAIT † T1 IOZ Down uPP Channel 0 Wait

This uPP pin has a primary function assigned to it as mentioned elsewhere in this table (see EMIF16).
UPP_CH1_CLK † T5 IOZ Down uPP Channel 1 Clock

This uPP pin has a primary function assigned to it as mentioned elsewhere in this table (see EMIF16).
UPP_CH1_START † U1 IOZ Down uPP Channel 1 Start

This uPP pin has a primary function assigned to it as mentioned elsewhere in this table (see EMIF16).
UPP_CH1_ENABLE † U2 IOZ Down uPP Channel 1 Enable

This uPP pin has a primary function assigned to it as mentioned elsewhere in this table (see EMIF16).
UPP_CH1_WAIT † U3 IOZ Down uPP Channel 1 Wait

This uPP pin has a primary function assigned to it as mentioned elsewhere in this table (see EMIF16).
UPPD00 † U4 IOZ Down uPP Data

This uPP pin has a primary function assigned to it as mentioned elsewhere in this table (see EMIF16).
UPPD01 † U5 IOZ Down
UPPD02 † V1 IOZ Down
UPPD03 † V2 IOZ Down
UPPD04 † V3 IOZ Down
UPPD05 † V4 IOZ Down
UPPD06 † W1 IOZ Down
UPPD07 † V5 IOZ Down
UPPD08 † W2 IOZ Down
UPPD09 † Y1 IOZ Down
UPPD10 † W4 IOZ Down
UPPD11 † Y2 IOZ Down
UPPD12 † W5 IOZ Down
UPPD13 † AA1 IOZ Down
UPPD14 † AB1 IOZ Down
UPPD15 † AA2 IOZ Down
UPPXD00 † K1 IOZ Down uPP Extended Data

This uPP ppn has a primary function assigned to it as mentioned elsewhere in this table (see EMIF16).
UPPXD01 † M3 IOZ Down
UPPXD02 † L2 IOZ Down
UPPXD03 † P5 IOZ Down
UPPXD04 † L1 IOZ Down
UPPXD05 † P4 IOZ Down
UPPXD06 † M2 IOZ Down
UPPXD07 † M1 IOZ Down
UPPXD08 † N2 IOZ Down
UPPXD09 † P3 IOZ Down
UPPXD10 † N1 IOZ Down
UPPXD11 † P2 IOZ Down
UPPXD12 † P1 IOZ Down
UPPXD13 † R5 IOZ Down
UPPXD14 † R3 IOZ Down
UPPXD15 † R4 IOZ Down
pEMU
EMU00 V24 IOZ Up Emulation and Trace Port
EMU01 V25 IOZ Up
EMU02 W25 IOZ Up
EMU03 W23 IOZ Up
EMU04 W24 IOZ Up
EMU05 Y25 IOZ Up
EMU06 Y24 IOZ Up
EMU07 Y23 IOZ Up
EMU08 W22 IOZ Up
EMU09 Y22 IOZ Up
EMU10 AA24 IOZ Up
EMU11 AA25 IOZ Up
EMU12 AB25 IOZ Up
EMU13 AC25 IOZ Up
EMU14 AA23 IOZ Up
EMU15 AB22 IOZ Up
EMU16 AD25 IOZ Up
EMU17 AC24 IOZ Up
EMU18 Y21 IOZ Up
General-Purpose Input/Output (GPIO)
GPIO00 T25 IOZ Up General-Purpose Input/Output

These GPIO pins have secondary functions assigned to them as mentioned elsewhere in this table (see Boot Configuration Pins).
GPIO01 R25 IOZ Down
GPIO02 R23 IOZ Down
GPIO03 U25 IOZ Down
GPIO04 T23 IOZ Down
GPIO05 U24 IOZ Down
GPIO06 T22 IOZ Down
GPIO07 R21 IOZ Down
GPIO08 U22 IOZ Down
GPIO09 U23 IOZ Down
GPIO10 V23 IOZ Down
GPIO11 U21 IOZ Down
GPIO12 T21 IOZ Down
GPIO13 V22 IOZ Down
GPIO14 W21 IOZ Down
GPIO15 V21 IOZ Down
GPIO16 † AD20 IOZ Down General-Purpose Input/Output

This GPIO pin has a primary function assigned to it as mentioned elsewhere in this table (see Timer) and a tertiary function assigned to it as mentioned elsewhere in this table (see Boot Configuration Pins).
GPIO17 † AE21 IOZ Down General-Purpose Input/Output

These GPIO pins have primary functions assigned to them as mentioned elsewhere in this table (see Timer).
GPIO18 † AC19 IOZ Down
GPIO19 † AE20 IOZ Down
GPIO20 † AB15 IOZ Down General-Purpose Input/Output

These GPIO pins have primary functions assigned to them as mentioned elsewhere in this table (see UART).
GPIO21 † AA15 IOZ Down
GPIO22 † AC17 IOZ Down
GPIO23 † AB17 IOZ Down
GPIO24 † AC14 IOZ Down
GPIO25 † AC15 IOZ Down
GPIO26 † AE16 IOZ Down
GPIO27 † AD15 IOZ Down
GPIO28 † AA12 IOZ Up General-Purpose Input/Output

These GPIO pins have primary functions assigned to them as mentioned elsewhere in this table (see SPI).
GPIO29 † AA14 IOZ Up
GPIO30 † AB14 IOZ Down
GPIO31 † AB13 IOZ Down
HyperLink
MCMRXN0 P24 I Serial HyperLink Receive Data
MCMRXP0 N24 I
MCMRXN1 M25 I
MCMRXP1 N25 I
MCMRXN2 J25 I
MCMRXP2 K25 I
MCMRXN3 K24 I
MCMRXP3 L24 I
MCMTXN0 P22 O Serial HyperLink Transmit Data
MCMTXP0 N22 O
MCMTXN1 N21 O
MCMTXP1 M21 O
MCMTXN2 K22 O
MCMTXP2 L22 O
MCMTXN3 J21 O
MCMTXP3 K21 O
MCMRXFLCLK B24 O Down Serial HyperLink Sideband Signals
MCMRXFLDAT C24 O Down
MCMTXFLCLK E25 I Down
MCMTXFLDAT D25 I Down
MCMRXPMCLK E24 I Down
MCMRXPMDAT D24 I Down
MCMTXPMCLK F24 O Down
MCMTXPMDAT G24 O Down
MCMREFCLKOUTP G25 O HyperLink Reference clock output for daisy chain connection
MCMREFCLKOUTN F25 O
I2C
SCL AA17 IOZ I2C Clock
SDA AA18 IOZ I2C Data
JTAG
TCK AD17 I Up JTAG Clock Input
TDI AE17 I Up JTAG Data Input
TDO AD19 OZ Up JTAG Data Output
TMS AE18 I Up JTAG Test Mode Input
TRST AB19 I Down JTAG Reset
McBSP
CLKR0 AA21 IOZ Down McBSP Receive Clock
CLKX0 Y20 IOZ Down McBSP Transmit Clock
CLKS0 AC23 IOZ Down McBSP Slow Clock
FSR0 AD24 IOZ Down McBSP Receive Frame Sync
FSX0 AA20 IOZ Down McBSP Transmit Frame Sync
DR0 AB21 I Down McBSP Receive Data
DX0 AC22 OZ Down McBSP Transmit Data
CLKR1 AD23 IOZ Down McBSP Receive Clock
CLKX1 AE24 IOZ Down McBSP Transmit Clock
CLKS1 AC21 IOZ Down McBSP Slow Clock
FSR1 AD22 IOZ Down McBSP Receive Frame Sync
FSX1 AE23 IOZ Down McBSP Transmit Frame Sync
DR1 AD21 I Down McBSP Receive Data
DX1 AE22 OZ Down McBSP Transmit Data
MDIO
MDIO AB16 IOZ Up MDIO Data
MDCLK AA16 O Down MDIO Clock
PCIe
PCIERXN0 AE12 I PCIexpress Receive Data (2 links)
PCIERXP0 AE11 I
PCIERXN1 AD10 I
PCIERXP1 AD11 I
PCIETXN0 AC12 O PCIexpress Transmit Data (2 links)
PCIETXP0 AC11 O
PCIETXN1 AB11 O
PCIETXP1 AB10 O
Serial RapidIO
RIORXN0 AE9 I Serial RapidIO Receive Data (4 links)
RIORXP0 AE8 I
RIORXN1 AD8 I
RIORXP1 AD7 I
RIORXN2 AE5 I
RIORXP2 AE6 I
RIORXN3 AD4 I
RIORXP3 AD5 I
RIOTXN0 AC9 O Serial RapidIO Receive Data (4 links)
RIOTXP0 AC8 O
RIOTXN1 AB7 O
RIOTXP1 AB8 O
RIOTXN2 AC5 O
RIOTXP2 AC6 O
RIOTXN3 AB4 O
RIOTXP3 AB5 O
SGMII
SGMII0RXN AE2 I Ethernet MAC SGMII Receive Data
SGMII0RXP AE3 I
SGMII0TXN AC2 O Ethernet MAC SGMII Transmit Data
SGMII0TXP AC3 O
SmartReflex
VCNTL0 E22 OZ Voltage Control Outputs to variable core power supply. These are open-drain output buffers.
VCNTL1 E23 OZ
VCNTL2 F23 OZ
VCNTL3 G23 OZ
SPI
SPISCS0 AA12 OZ Up SPI Interface Enable 0

This SPI pin has a secondary function assigned to it as mentioned elsewhere in this table (see GPIO).
SPISCS1 AA14 OZ Up SPI Interface Enable 1

This SPI pin has a secondary function assigned to it as mentioned elsewhere in this table (see GPIO).
SPICLK AA13 OZ Down SPI Clock
SPIDIN AB14 I Down SPI Data In

This SPI pin has a secondary function assigned to it as mentioned elsewhere in this table (see GPIO).
SPIDOUT AB13 OZ Down SPI Data Out

This SPI pin has a secondary function assigned to it as mentioned elsewhere in this table (see GPIO).
Timer
TIMI0 AD20 I Down Timer Inputs

This SPI pin has a secondary function assigned to it as mentioned elsewhere in this table (see GPIO).
TIMI1 AE21 I Down
TIMO0 AC19 OZ Down Timer Outputs

These Timer pins have secondary functions assigned to them as mentioned elsewhere in this table
TIMO1 AE20 OZ Down
UART
UARTRXD AB15 I Down UART Serial Data In

This SPI pin has a secondary function assigned to it as mentioned elsewhere in this table (see GPIO).
UARTTXD AA15 OZ Down UART Serial Data Out

This SPI pin has a secondary function assigned to it as mentioned elsewhere in this table (see GPIO).
UARTCTS AC17 I Down UART Clear To Send

This SPI pin has a secondary function assigned to it as mentioned elsewhere in this table (see GPIO).
UARTRTS AB17 OZ Down UART Request To Send

This SPI pin has a secondary function assigned to it as mentioned elsewhere in this table (see GPIO).
UARTRXD1 AC14 I Down UART Serial Data In

This SPI pin has a secondary function assigned to it as mentioned elsewhere in this table (see GPIO).
UARTTXD1 AC15 OZ Down UART Serial Data Out

This SPI pin has a secondary function assigned to it as mentioned elsewhere in this table (see GPIO).
UARTCTS1 AE16 I Down UART Clear To Send

This SPI pin has a secondary function assigned to it as mentioned elsewhere in this table (see GPIO).
UARTRTS1 AD15 OZ Down UART Request To Send

This SPI pin has a secondary function assigned to it as mentioned elsewhere in this table (see GPIO).
Reserved
RSV01 AA22 IOZ Up Reserved - pullup to DVDD18
RSV02 J3 OZ Down Reserved - leave unconnected
RSV03 H2 OZ Down Reserved - leave unconnected
RSV04 AC18 O Reserved - leave unconnected
RSV05 AB18 O Reserved - leave unconnected
RSV06 B23 O Reserved - leave unconnected
RSV07 A23 O Reserved - leave unconnected
RSV08 Y19 OZ Down Reserved - leave unconnected
RSV09 C23 OZ Down Reserved - leave unconnected
RSV10 G22 A Reserved - connect to GND
RSV11 H22 A Reserved - leave unconnected
RSV12 Y5 A Reserved - leave unconnected
RSV13 Y4 A Reserved - leave unconnected
RSV14 F21 A Reserved - leave unconnected
RSV15 G21 A Reserved - leave unconnected
RSV16 J20 A Reserved - leave unconnected
RSV17 AA7 A Reserved - leave unconnected
RSV18 AA11 A Reserved - leave unconnected
RSV19 AB3 A Reserved - leave unconnected
RSV20 F22 IOZ Reserved - leave unconnected
RSV21 D23 IOZ Reserved - leave unconnected
RSV0A G19 A Reserved - leave unconnected
RSV0B G20 A Reserved - leave unconnected

Table 4-3 Terminal Functions — Power and Ground

SUPPLY BALL NO. VOLTS DESCRIPTION
AVDDA1 Y15 1.8 PLL Supply - CORE_PLL
AVDDA2 F20 1.8 PLL Supply - DDR3_PLL
CVDD H9, H11, H13, H15, H17, J10, J12, J14, J16, K11, K13, K15, L8, L10, L12, L14, L16, L18, M9, M11, M13, M15, M17, N8, N10, N12, N14, N16, N18, P9, P11, P13, P15, P17, P19, R10, R12, R14, R16, R18, T11, T13, T15, U10, U12, U14, U16, V9, V11, V13, V15, V17 0.85 to 1.1 SmartReflex core supply voltage
CVDD1 J8, J18, K9, K17, T9, T17, U8, U18 1.0 Fixed core supply voltage for memory array
DVDD15 B10, C6, C17, C21, D2, D4, D8, D13, D15, D19, F7, F9, F11, F13, F17, F19, G8, G10, G12, G14, G16, G18 1.5 DDR I/O supply
DVDD18 A24, E21, G3, G6, H7, H19, H24, J6, K3, K7, L6, M7, N3, N6, P7, R6, R20, T3, T7, T19, T24, U6, U20, V7, V19, W6, W14, W16, W18, W20, Y3, Y13, Y17, AB23, AC16, AC20 1.8 I/O supply
VDDR1 M20 1.5 HyperLink SerDes regulator supply
VDDR2 AA9 1.5 PCIe SerDes regulator supply
VDDR3 AA3 1.5 SGMII SerDes regulator supply
VDDR4 AA5 1.5 SRIO SerDes regulator supply
VDDT1 K19, L20, M19, N20 1.0 HyperLink SerDes termination supply
VDDT2 W8, W10, W12, Y7, Y9, Y11 1.0 SGMII/SRIO/PCIe SerDes termination supply
VREFSSTL E12 0.75 DDR3 reference voltage
VSS A1, A10, A25, B6, B17, C2, C4, C8, C13, C15, C19, D21, E11, F3, F6, F8, F10, F12, F14, F16, F18, G7, G9, G11, G13, G15, G17, H6, H8, H10, H12, H14, H16, H18, H20, H21, H23, H25, J7, J9, J11, J13, J15, J17, J19, J22, J23, J24, K2, K6, K8, K10, K12, K14, K16, K18, K20, K23, L7, L9, L11, L13, L15, L17, L19, L21, L23, L25, M6, M8, M10, M12, M14, M16, M18, M22, M23, M24, N4, N7, N9, N11, N13, N15, N17, N19, N23, P6, P8, P10, P12, P14, P16, P18, P20, P21, P23, P25, R7, R8, R9, R11, R13, R15, R17, R19, R22, R24, T2, T6, T8, T10, T12, T14, T16, T18, T20, U7, U9, U11, U13, U15, U17, U19, V6, V8, V10, V12, V14, V16, V18, V20, W3, W7, W9, W11, W13, W15, W17, W19, Y6, Y8, Y10, Y12, Y14, Y16, AA4, AA6, AA8, AA10, AB2, AB6, AB9, AB12, AB20, AB24, AC1, AC4, AC7, AC10, AC13, AD1, AD2, AD3, AD6, AD9, AD12, AD16, AE1, AE4, AE7, AE10, AE13, AE25 GND Ground

Table 4-4 Terminal Functions — By Signal Name

SIGNAL NAME BALL NUMBER SIGNAL NAME BALL NUMBER SIGNAL NAME BALL NUMBER
AVDDA1 Y15 DDRA09 E20 DDRD22 C5
AVDDA2 F20 DDRA10 E19 DDRD23 D5
BOOTCOMPLETE H3 DDRA11 B20 DDRD24 E2
BOOTMODE00 † R25 DDRA12 D18 DDRD25 F2
BOOTMODE01 † R23 DDRA13 C20 DDRD26 B1
BOOTMODE02 † U25 DDRA14 E18 DDRD27 C1
BOOTMODE03 † T23 DDRA15 E17 DDRD28 D1
BOOTMODE04 † U24 DDRBA0 C18 DDRD29 D3
BOOTMODE05 † T22 DDRBA1 D17 DDRD30 C3
BOOTMODE06 † R21 DDRBA2 B19 DDRD31 E3
BOOTMODE07 † U22 DDRCAS D14 DDRDQM0 A8
BOOTMODE08 † U23 DDRCB00 D11 DDRDQM1 E7
BOOTMODE09 † V23 DDRCB01 B12 DDRDQM2 F5
BOOTMODE10 † U21 DDRCB02 C11 DDRDQM3 E1
BOOTMODE11 † T21 DDRCB03 A12 DDRDQM8 C12
BOOTMODE12 † V22 DDRCE0 B15 DDRDQS0N C10
CLKR0 AA21 DDRCE1 C14 DDRDQS0P D10
CLKR1 AD23 DDRCKE0 A16 DDRDQS1N A7
CLKS0 AC23 DDRCKE1 A20 DDRDQS1P B7
CLKS1 AC21 DDRCLKN B22 DDRDQS2N A4
CLKX0 Y20 DDRCLKOUTN0 B14 DDRDQS2P B4
CLKX1 AE24 DDRCLKOUTN1 B21 DDRDQS3N B2
CORECLKN AE19 DDRCLKOUTP0 A14 DDRDQS3P A2
CORECLKP AD18 DDRCLKOUTP1 A21 DDRDQS8N A13
CORESEL0 J5 DDRCLKP A22 DDRDQS8P B13
CORESEL1 G5 DDRD00 A9 DDRODT0 E14
CVDD H9, H11, H13, H15, H17, J10, J12, J14, J16, K11, K13, K15, L8, L10, L12, L14, L16, L18, M9, M11, M13, M15, M17, N8, N10, N12, N14, N16, N18, P9, P11, P13, P15, P17, P19, R10, R12, R14, R16, R18, T11, T13, T15, U10, U12, U14, U16, V9, V11, V13, V15, V17 DDRD01 C9 DDRODT1 D12
DDRD02 D9 DDRRAS A15
DDRD03 B9 DDRRESET B16
DDRD04 E9 DDRSLRATE0 C22
DDRD05 E10 DDRSLRATE1 D22
DDRD06 A11 DDRWE E13
DDRD07 B11 DR0 AB21
DDRD08 E6 DR1 AD21
DDRD09 E8 DVDD15 B10, C6, C17, C21, D2, D4, D8, D13, D15, D19, F7, F9, F11, F13, F17, F19, G8, G10, G12, G14, G16, G18
DDRD10 A6
CVDD1 J8, J18, K9, K17, T9, T17, U8, U18 DDRD11 A5
DDRD12 D6
DDRA00 D16 DDRD13 C7
DDRA01 A19 DDRD14 D7 DVDD18 A24, E21, G3, G6, H7, H19, H24, J6, K3, K7, L6, M7, N3, N6, P7, R6, R20, T3, T7, T19, T24, U6, U20, V7, V19, W6, W14, W16, W18, W20, Y3, Y13, Y17, AB23, AC16, AC20
DDRA02 E16 DDRD15 B8
DDRA03 E15 DDRD16 E5
DDRA04 B18 DDRD17 B3
DDRA05 A17 DDRD18 F4
DDRA06 C16 DDRD19 E4
DDRA07 A18 DDRD20 A3
DDRA08 D20 DDRD21 B5
DX0 AC22 EMIFD15 AA2 GPIO18 † AC19
DX1 AE22 EMIFOE L4 GPIO19 † AE20
EMIFA00 K1 EMIFRNW L5 GPIO20 † AB15
EMIFA01 M3 EMIFWAIT0 N5 GPIO21 † AA15
EMIFA02 L2 EMIFWAIT1 M4 GPIO22 † AC17
EMIFA03 P5 EMIFWE K4 GPIO23 † AB17
EMIFA04 L1 EMU00 V24 GPIO24 † AC14
EMIFA05 P4 EMU01 V25 GPIO25 † AC15
EMIFA06 M2 EMU02 W25 GPIO26 † AE16
EMIFA07 M1 EMU03 W23 GPIO27 † AD15
EMIFA08 N2 EMU04 W24 GPIO28 † AA12
EMIFA09 P3 EMU05 Y25 GPIO29 † AA14
EMIFA10 N1 EMU06 Y24 GPIO30 † AB14
EMIFA11 P2 EMU07 Y23 GPIO31 † AB13
EMIFA12 P1 EMU08 W22 HOUT G2
EMIFA13 R5 EMU09 Y22 LENDIAN † T25
EMIFA14 R3 EMU10 AA24 LRESETNMIEN F1
EMIFA15 R4 EMU11 AA25 LRESET G4
EMIFA16 R2 EMU12 AB25 MCMCLKN B25
EMIFA17 R1 EMU13 AC25 MCMCLKP C25
EMIFA18 T4 EMU14 AA23 MCMREFCLKOUTN F25
EMIFA19 T1 EMU15 AB22 MCMREFCLKOUTP G25
EMIFA20 T5 EMU16 AD25 MCMRXFLCLK B24
EMIFA21 U1 EMU17 AC24 MCMRXFLDAT C24
EMIFA22 U2 EMU18 Y21 MCMRXN0 P24
EMIFA23 U3 FSR0 AD24 MCMRXN1 M25
EMIFBE0 J1 FSR1 AD22 MCMRXN2 J25
EMIFBE1 L3 FSX0 AA20 MCMRXN3 K24
EMIFCE0 K5 FSX1 AE23 MCMRXP0 N24
EMIFCE1 G1 GPIO00 T25 MCMRXP1 N25
EMIFCE2 J2 GPIO01 R25 MCMRXP2 K25
EMIFCE3 M5 GPIO02 R23 MCMRXP3 L24
EMIFD00 U4 GPIO03 U25 MCMRXPMCLK E24
EMIFD01 U5 GPIO04 T23 MCMRXPMDAT D24
EMIFD02 V1 GPIO05 U24 MCMTXFLCLK E25
EMIFD03 V2 GPIO06 T22 MCMTXFLDAT D25
EMIFD04 V3 GPIO07 R21 MCMTXN0 P22
EMIFD05 V4 GPIO08 U22 MCMTXN1 N21
EMIFD06 W1 GPIO09 U23 MCMTXN2 K22
EMIFD07 V5 GPIO10 V23 MCMTXN3 J21
EMIFD08 W2 GPIO11 U21 MCMTXP0 N22
EMIFD09 Y1 GPIO12 T21 MCMTXP1 M21
EMIFD10 W4 GPIO13 V22 MCMTXP2 L22
EMIFD11 Y2 GPIO14 W21 MCMTXP3 K21
EMIFD12 W5 GPIO15 V21 MCMTXPMCLK F24
EMIFD13 AA1 GPIO16 † AD20 MCMTXPMDAT G24
EMIFD14 AB1 GPIO17 † AE21 MDCLK AA16
MDIO AB16 RSV12 Y5 UPP_CH0_WAIT † T1
NMI H1 RSV13 Y4 UPP_CH1_CLK † T5
PCIECLKN AE15 RSV14 F21 UPP_CH1_ENABLE † U2
PCIECLKP AD14 RSV15 G21 UPP_CH1_START † U1
PCIERXN0 AE12 RSV16 J20 UPP_CH1_WAIT † U3
PCIERXN1 AD10 RSV17 AA7 UPPD00 † U4
PCIERXP0 AE11 RSV18 AA11 UPPD01 † U5
PCIERXP1 AD11 RSV19 AB3 UPPD02 † V1
PCIESSEN ‡ AD20 RSV20 F22 UPPD03 † V2
PCIETXN0 AC12 RSV21 D23 UPPD04 † V3
PCIETXN1 AB11 SCL AA17 UPPD05 † V4
PCIETXP0 AC11 SDA AA18 UPPD06 † W1
PCIETXP1 AB10 SGMII0RXN AE2 UPPD07 † V5
POR Y18 SGMII0RXP AE3 UPPD08 † W2
PTV15 F15 SGMII0TXN AC2 UPPD09 † Y1
RESETFULL J4 SGMII0TXP AC3 UPPD10 † W4
RESETSTAT H5 SPICLK AA13 UPPD11 † Y2
RESET H4 SPIDIN AB14 UPPD12 † W5
RIORXN0 AE9 SPIDOUT AB13 UPPD13 † AA1
RIORXN1 AD8 SPISCS0 AA12 UPPD14 † AB1
RIORXN2 AE5 SPISCS1 AA14 UPPD15 † AA2
RIORXN3 AD4 SRIOSGMIICLKN AE14 UPPXD00 † K1
RIORXP0 AE8 SRIOSGMIICLKP AD13 UPPXD01 † M3
RIORXP1 AD7 SYSCLKOUT AA19 UPPXD02 † L2
RIORXP2 AE6 TCK AD17 UPPXD03 † P5
RIORXP3 AD5 TDI AE17 UPPXD04 † L1
RIOTXN0 AC9 TDO AD19 UPPXD05 † P4
RIOTXN1 AB7 TIMI0 AD20 UPPXD06 † M2
RIOTXN2 AC5 TIMI1 AE21 UPPXD07 † M1
RIOTXN3 AB4 TIMO0 AC19 UPPXD08 † N2
RIOTXP0 AC8 TIMO1 AE20 UPPXD09 † P3
RIOTXP1 AB8 TMS AE18 UPPXD10 † N1
RIOTXP2 AC6 TRST AB19 UPPXD11 † P2
RIOTXP3 AB5 UARTCTS AC17 UPPXD12 † P1
RSV01 AA22 UARTCTS1 AE16 UPPXD13 † R5
RSV02 J3 UARTRTS AB17 UPPXD14 † R3
RSV03 H2 UARTRTS1 AD15 UPPXD15 † R4
RSV04 AC18 UARTRXD AB15 VCNTL0 E22
RSV05 AB18 UARTRXD1 AC14 VCNTL1 E23
RSV06 B23 UARTTXD AA15 VCNTL2 F23
RSV07 A23 UARTTXD1 AC15 VCNTL3 G23
RSV08 Y19 UPP_2XTXCLK † M4 VDDR1 M20
RSV09 C23 UPP_CH0_CLK † R2 VDDR2 AA9
RSV0A G19 UPP_CH0_
ENABLE †		 T4 VDDR3 AA3
RSV0B G20 VDDR4 AA5
RSV10 G22 UPP_CH0_
START †		 R1 VDDT1 K19, L20, M19, N20
RSV11 H22
VDDT2 W8, W10, W12, Y7, Y9, Y11
VDDT1 N20
VDDT2 W10
VDDT2 W12
VDDT2 Y7
VDDT2 Y9
VDDT2 Y11
VREFSSTL E12
VSS A1, A10, A25, B6, B17, C2, C4, C8, C13, C15, C19, D21, E11, F3, F6, F8, F10, F12, F14, F16, F18, G7, G9, G11, G13, G15, G17, H6, H8, H10, H12, H14, H16, H18, H20, H21, H23, H25, J7, J9, J11, J13, J15, J17, J19, J22, J23, J24, K2, K6, K8, K10, K12, K14, K16, K18, K20, K23, L7, L9, L11, L13, L15, L17, L19, L21, L23, L25, M6, M8, M10, M12, M14, M16, M18, M22, M23, M24, N4, N7, N9, N11, N13, N15, N17, N19, N23, P6, P8, P10, P12, P14, P16, P18, P20, P21, P23, P25, R7, R8, R9, R11, R13, R15, R17, R19, R22, R24, T2, T6, T8, T10, T12, T14, T16, T18, T20, U7, U9, U11, U13, U15, U17, U19, V6, V8, V10, V12, V14, V16, V18, V20, W3, W7, W9, W11, W13, W15, W17, W19, Y6, Y8, Y10, Y12, Y14, Y16, AA4, AA6, AA8, AA10, AB2, AB6, AB9, AB12, AB20, AB24, AC1, AC4, AC7, AC10, AC13, AD1, AD2, AD3, AD6, AD9, AD12, AD16, AE1, AE4, AE7, AE10, AE13, AE25

Table 4-5 Terminal Functions — By Ball Number

BALL NUMBER SIGNAL NAME BALL NUMBER SIGNAL NAME BALL NUMBER SIGNAL NAME
A1 VSS B23 RSV06 D20 DDRA08
A2 DDRDQS3P B24 MCMRXFLCLK D21 VSS
A3 DDRD20 B25 MCMCLKN D22 DDRSLRATE1
A4 DDRDQS2N C1 DDRD27 D23 RSV21
A5 DDRD11 C2 VSS D24 MCMRXPMDAT
A6 DDRD10 C3 DDRD30 D25 MCMTXFLDAT
A7 DDRDQS1N C4 VSS E1 DDRDQM3
A8 DDRDQM0 C5 DDRD22 E2 DDRD24
A9 DDRD00 C6 DVDD15 E3 DDRD31
A10 VSS C7 DDRD13 E4 DDRD19
A11 DDRD06 C8 VSS E5 DDRD16
A12 DDRCB03 C9 DDRD01 E6 DDRD08
A13 DDRDQS8N C10 DDRDQS0N E7 DDRDQM1
A14 DDRCLKOUTP0 C11 DDRCB02 E8 DDRD09
A15 DDRRAS C12 DDRDQM8 E9 DDRD04
A16 DDRCKE0 C13 VSS E10 DDRD05
A17 DDRA05 C14 DDRCE1 E11 VSS
A18 DDRA07 C15 VSS E12 VREFSSTL
A19 DDRA01 C16 DDRA06 E13 DDRWE
A20 DDRCKE1 C17 DVDD15 E14 DDRODT0
A21 DDRCLKOUTP1 C18 DDRBA0 E15 DDRA03
A22 DDRCLKP C19 VSS E16 DDRA02
A23 RSV07 C20 DDRA13 E17 DDRA15
A24 DVDD18 C21 DVDD15 E18 DDRA14
A25 VSS C22 DDRSLRATE0 E19 DDRA10
B1 DDRD26 C23 RSV09 E20 DDRA09
B2 DDRDQS3N C24 MCMRXFLDAT E21 DVDD18
B3 DDRD17 C25 MCMCLKP E22 VCNTL0
B4 DDRDQS2P D1 DDRD28 E23 VCNTL1
B5 DDRD21 D2 DVDD15 E24 MCMRXPMCLK
B6 VSS D3 DDRD29 E25 MCMTXFLCLK
B7 DDRDQS1P D4 DVDD15 F1 LRESETNMIEN
B8 DDRD15 D5 DDRD23 F2 DDRD25
B9 DDRD03 D6 DDRD12 F3 VSS
B10 DVDD15 D7 DDRD14 F4 DDRD18
B11 DDRD07 D8 DVDD15 F5 DDRDQM2
B12 DDRCB01 D9 DDRD02 F6 VSS
B13 DDRDQS8P D10 DDRDQS0P F7 DVDD15
B14 DDRCLKOUTN0 D11 DDRCB00 F8 VSS
B15 DDRCE0 D12 DDRODT1 F9 DVDD15
B16 DDRRESET D13 DVDD15 F10 VSS
B17 VSS D14 DDRCAS F11 DVDD15
B18 DDRA04 D15 DVDD15 F12 VSS
B19 DDRBA2 D16 DDRA00 F13 DVDD15
B20 DDRA11 D17 DDRBA1 F14 VSS
B21 DDRCLKOUTN1 D18 DDRA12 F15 PTV15
B22 DDRCLKN D19 DVDD15 F16 VSS
F17 DVDD15 H14 VSS K10 VSS
F18 VSS H15 CVDD K11 CVDD
F19 DVDD15 H16 VSS K12 VSS
F20 AVDDA2 H17 CVDD K13 CVDD
F21 RSV14 H18 VSS K14 VSS
F22 RSV20 H19 DVDD18 K15 CVDD
F23 VCNTL2 H20 VSS K16 VSS
F24 MCMTXPMCLK H21 VSS K17 CVDD1
F25 MCMREFCLKOUTN H22 RSV11 K18 VSS
G1 EMIFCE1 H23 VSS K19 VDDT1
G2 HOUT H24 DVDD18 K20 VSS
G3 DVDD18 H25 VSS K21 MCMTXP3
G4 LRESET J1 EMIFBE0 K22 MCMTXN2
G5 CORESEL1 J2 EMIFCE2 K23 VSS
G6 DVDD18 J3 RSV02 K24 MCMRXN3
G7 VSS J4 RESETFULL K25 MCMRXP2
G8 DVDD15 J5 CORESEL0 L1 EMIFA04
G9 VSS J6 DVDD18 L1 UPPXD04 †
G10 DVDD15 J7 VSS L2 EMIFA02
G11 VSS J8 CVDD1 L2 UPPXD02 †
G12 DVDD15 J9 VSS L3 EMIFBE1
G13 VSS J10 CVDD L4 EMIFOE
G14 DVDD15 J11 VSS L5 EMIFRNW
G15 VSS J12 CVDD L6 DVDD18
G16 DVDD15 J13 VSS L7 VSS
G17 VSS J14 CVDD L8 CVDD
G18 DVDD15 J15 VSS L9 VSS
G19 RSV0A J16 CVDD L10 CVDD
G20 RSV0B J17 VSS L11 VSS
G21 RSV15 J18 CVDD1 L12 CVDD
G22 RSV10 J19 VSS L13 VSS
G23 VCNTL3 J20 RSV16 L14 CVDD
G24 MCMTXPMDAT J21 MCMTXN3 L15 VSS
G25 MCMREFCLKOUTP J22 VSS L16 CVDD
H1 NMI J23 VSS L17 VSS
H2 RSV03 J24 VSS L18 CVDD
H3 BOOTCOMPLETE J25 MCMRXN2 L19 VSS
H4 RESET K1 EMIFA00 L20 VDDT1
H5 RESETSTAT K1 UPPXD00 † L21 VSS
H6 VSS K2 VSS L22 MCMTXP2
H7 DVDD18 K3 DVDD18 L23 VSS
H8 VSS K4 EMIFWE L24 MCMRXP3
H9 CVDD K5 EMIFCE0 L25 VSS
H10 VSS K6 VSS M1 EMIFA07
H11 CVDD K7 DVDD18 M1 UPPXD07 †
H12 VSS K8 VSS M2 EMIFA06
H13 CVDD K9 CVDD1 M2 UPPXD06 †
M3 EMIFA01 N21 MCMTXN1 R8 VSS
M3 UPPXD01 † N22 MCMTXP0 R9 VSS
M4 EMIFWAIT1 N23 VSS R10 CVDD
M4 UPP2XTXCLK † N24 MCMRXP0 R11 VSS
M5 EMIFCE3 N25 MCMRXP1 R12 CVDD
M6 VSS P1 EMIFA12 R13 VSS
M7 DVDD18 P1 UPPXD12 † R14 CVDD
M8 VSS P2 EMIFA11 R15 VSS
M9 CVDD P2 UPPXD11 † R16 CVDD
M10 VSS P3 EMIFA09 R17 VSS
M11 CVDD P3 UPPXD09 † R18 CVDD
M12 VSS P4 EMIFA05 R19 VSS
M13 CVDD P4 UPPXD05 † R20 DVDD18
M14 VSS P5 EMIFA03 R21 GPIO07
M15 CVDD P5 UPPXD03 † R21 BOOTMODE06 †
M16 VSS P6 VSS R22 VSS
M17 CVDD P7 DVDD18 R23 GPIO02
M18 VSS P8 VSS R23 BOOTMODE01 †
M19 VDDT1 P9 CVDD R24 VSS
M20 VDDR1 P10 VSS R25 GPIO01
M21 MCMTXP1 P11 CVDD R25 BOOTMODE00 †
M22 VSS P12 VSS T1 EMIFA19
M23 VSS P13 CVDD T1 UPP_CH0_WAIT †
M24 VSS P14 VSS T2 VSS
M25 MCMRXN1 P15 CVDD T3 DVDD18
N1 EMIFA10 P16 VSS T4 EMIFA18
N1 UPPXD10 † P17 CVDD T4 UPP_CH0_ENABLE †
N2 EMIFA08 P18 VSS T5 EMIFA20
N2 UPPXD08 † P19 CVDD T5 UPP_CH1_CLK †
N3 DVDD18 P20 VSS T6 VSS
N4 VSS P21 VSS T7 DVDD18
N5 EMIFWAIT0 P22 MCMTXN0 T8 VSS
N6 DVDD18 P23 VSS T9 CVDD1
N7 VSS P24 MCMRXN0 T10 VSS
N8 CVDD P25 VSS T11 CVDD
N9 VSS R1 EMIFA17 T12 VSS
N10 CVDD R1 UPP_CH0_START † T13 CVDD
N11 VSS R2 EMIFA16 T14 VSS
N12 CVDD R2 UPP_CH0_CLK † T15 CVDD
N13 VSS R3 EMIFA14 T16 VSS
N14 CVDD R3 UPPXD14 † T17 CVDD1
N15 VSS R4 EMIFA15 T18 VSS
N16 CVDD R4 UPPXD15 † T19 DVDD18
N17 VSS R5 EMIFA13 T20 VSS
N18 CVDD R5 UPPXD13 † T21 GPIO12
N19 VSS R6 DVDD18 T21 BOOTMODE11 †
N20 VDDT1 R7 VSS T22 GPIO06
T22 BOOTMODE05 † V3 UPPD04 † W16 DVDD18
T23 GPIO04 V4 EMIFD05 W17 VSS
T23 BOOTMODE03 † V4 UPPD05 † W18 DVDD18
T24 DVDD18 V5 EMIFD07 W19 VSS
T25 GPIO00 V5 UPPD07 † W20 DVDD18
T25 LENDIAN † V6 VSS W21 GPIO14 †
U1 EMIFA21 V7 DVDD18 W21 PCIESSMODE0 †
U1 UPP_CH1_START † V8 VSS W22 EMU08
U2 EMIFA22 V9 CVDD W23 EMU03
U2 UPP_CH1_ENABLE † V10 VSS W24 EMU04
V11 CVDD W25 EMU02
U3 EMIFA23 V12 VSS Y1 EMIFD09
U3 UPP_CH1_WAIT † V13 CVDD Y1 UPPD09 †
U4 EMIFD00 V14 VSS Y2 EMIFD11
U4 UPPD00 † V15 CVDD Y2 UPPD11 †
U5 EMIFD01 V16 VSS Y3 DVDD18
U5 UPPD01 † V17 CVDD Y4 RSV13
U6 DVDD18 V18 VSS Y5 RSV12
U7 VSS V19 DVDD18 Y6 VSS
U8 CVDD1 V20 VSS Y7 VDDT2
U9 VSS V21 GPIO15 Y8 VSS
U10 CVDD V21 PCIESSMODE1 † Y9 VDDT2
U11 VSS V22 GPIO13 Y10 VSS
U12 CVDD V22 BOOTMODE12 † Y11 VDDT2
U13 VSS V23 GPIO10 Y12 VSS
U14 CVDD V23 BOOTMODE09 † Y13 DVDD18
U15 VSS V24 EMU00 Y14 VSS
U16 CVDD V25 EMU01 Y15 AVDDA1
U17 VSS W1 EMIFD06 Y16 VSS
U18 CVDD1 W1 UPPD06 † Y17 DVDD18
U19 VSS W2 EMIFD08 Y18 POR
U20 DVDD18 W2 UPPD08 † Y19 RSV08
U21 GPIO11 W3 VSS Y20 CLKX0
U21 BOOTMODE10 † W4 EMIFD10 Y21 EMU18
U22 GPIO08 W4 UPPD10 † Y22 EMU09
U22 BOOTMODE07 † W5 EMIFD12 Y23 EMU07
U23 GPIO09 W5 UPPD12 † Y24 EMU06
U23 BOOTMODE08 † W6 DVDD18 Y25 EMU05
U24 GPIO05 W7 VSS AA1 EMIFD13
U24 BOOTMODE04 † W8 VDDT2 AA1 UPPD13 †
U25 GPIO03 W9 VSS AA2 EMIFD15
U25 BOOTMODE02 † W10 VDDT2 AA2 UPPD15 †
V1 EMIFD02 W11 VSS AA3 VDDR3
V1 UPPD02 † W12 VDDT2 AA4 VSS
V2 EMIFD03 W13 VSS AA5 VDDR4
V2 UPPD03 † W14 DVDD18 AA6 VSS
V3 EMIFD04 W15 VSS AA7 RSV17
AA8 VSS AB22 EMU15 AD15 UARTRTS1
AA9 VDDR2 AB23 DVDD18 AD15 GPIO27 †
AA10 VSS AB24 VSS AD16 VSS
AA11 RSV18 AB25 EMU12 AD17 TCK
AA12 SPISCS0 AC1 VSS AD18 CORECLKP
AA12 GPIO28 † AC2 SGMII0TXN AD19 TDO
AA13 SPICLK AC3 SGMII0TXP AD20 TIMI0
AA14 SPISCS1 AC4 VSS AD20 GPIO16 †
AA14 GPIO29 † AC5 RIOTXN2 AD20 PCIESSEN ‡
AA15 UARTTXD AC6 RIOTXP2 AD21 DR1
AA15 GPIO21 † AC7 VSS AD22 FSR1
AA16 MDCLK AC8 RIOTXP0 AD23 CLKR1
AA17 SCL AC9 RIOTXN0 AD24 FSR0
AA18 SDA AC10 VSS AD25 EMU16
AA19 SYSCLKOUT AC11 PCIETXP0 AE1 VSS
AA20 FSX0 AC12 PCIETXN0 AE2 SGMII0RXN
AA21 CLKR0 AC13 VSS AE3 SGMII0RXP
AA22 RSV01 AC14 UARTRXD1 AE4 VSS
AA23 EMU14 AC14 GPIO24 † AE5 RIORXN2
AA24 EMU10 AC15 UARTTXD1 AE6 RIORXP2
AA25 EMU11 AC15 GPIO25 † AE7 VSS
AB1 EMIFD14 AC16 DVDD18 AE8 RIORXP0
AB1 UPPD14 † AC17 UARTCTS AE9 RIORXN0
AB2 VSS AC17 GPIO22 † AE10 VSS
AB3 RSV19 AC18 RSV04 AE11 PCIERXP0
AB4 RIOTXN3 AC19 TIMO0 AE12 PCIERXN0
AB5 RIOTXP3 AC19 GPIO18 † AE13 VSS
AB6 VSS AC20 DVDD18 AE14 SRIOSGMIICLKN
AB7 RIOTXN1 AC21 CLKS1 AE15 PCIECLKN
AB8 RIOTXP1 AC22 DX0 AE16 UARTCTS1
AB9 VSS AC23 CLKS0 AE16 GPIO26 †
AB10 PCIETXP1 AC24 EMU17 AE17 TDI
AB11 PCIETXN1 AC25 EMU13 AE18 TMS
AB12 VSS AD1 VSS AE19 CORECLKN
AB13 SPIDOUT AD2 VSS AE20 TIMO1
AB13 GPIO31 † AD3 VSS AE20 GPIO19 †
AB14 SPIDIN AD4 RIORXN3 AE21 TIMI1
AB14 GPIO30 † AD5 RIORXP3 AE21 GPIO17 †
AB15 UARTRXD AD6 VSS AE22 DX1
AB15 GPIO20 † AD7 RIORXP1 AE23 FSX1
AB16 MDIO AD8 RIORXN1 AE24 CLKX1
AB17 UARTRTS AD9 VSS AE25 VSS
AB17 GPIO23 † AD10 PCIERXN1
AB18 RSV05 AD11 PCIERXP1
AB19 TRST AD12 VSS
AB20 VSS AD13 SRIOSGMIICLKP
AB21 DR0 AD14 PCIECLKP