SPRS814D March   2012  – October 2019 TMS320C6655 , TMS320C6657

PRODUCTION DATA.  

  1. 1 Device Overview
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Functional Block Diagram
  2. 2 Revision History
  3. 3 Device Comparison
    1. 3.1 Device Comparison
  4. 4 Terminal Configuration and Functions
    1. 4.1 Pin Diagram
    2. 4.2 Terminal Functions
  5. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Power Consumption Summary
    5. 5.5 Electrical Characteristics
    6. 5.6 Thermal Resistance Characteristics for [CZH/GZH] Package
    7. 5.7 Timing and Switching Characteristics
      1. 5.7.1  SmartReflex
        1. Table 5-1 SmartReflex 4-Pin VID Interface Switching Characteristics
      2. 5.7.2  Reset Electrical Data / Timing
        1. Table 5-2 Reset Timing Requirements
        2. Table 5-3 Reset Switching Characteristics Over Recommended Operating Conditions
        3. Table 5-4 Boot Configuration Timing Requirements
      3. 5.7.3  Main PLL Stabilization, Lock, and Reset Times
      4. 5.7.4  Main PLL Controller/SRIO/HyperLink/PCIe Clock Input Electrical Data/Timing
        1. Table 5-6 Main PLL Controller/SRIO/HyperLink/PCIe Clock Input Timing Requirements
      5. 5.7.5  DDR3 PLL Input Clock Electrical Data/Timing
        1. Table 5-7 DDR3 PLL DDRSYSCLK1(N|P) Timing Requirements
      6. 5.7.6  External Interrupts Electrical Data/Timing
        1. Table 5-8 NMI and Local Reset Timing Requirements
      7. 5.7.7  DDR3 Memory Controller Electrical Data/Timing
      8. 5.7.8  I2C Electrical Data/Timing
        1. 5.7.8.1 Inter-Integrated Circuits (I2C) Timing
          1. Table 5-9  I2C Timing Requirements
          2. Table 5-10 I2C Switching Characteristics
      9. 5.7.9  SPI Peripheral
        1. 5.7.9.1 SPI Timing
          1. Table 5-11 SPI Timing Requirements
          2. Table 5-12 SPI Switching Characteristics
      10. 5.7.10 HyperLink Electrical Data/Timing
        1. Table 5-13 HyperLink Peripheral Timing Requirements
        2. Table 5-14 HyperLink Peripheral Switching Characteristics
      11. 5.7.11 UART Peripheral
        1. Table 5-15 UART Timing Requirements
        2. Table 5-16 UART Switching Characteristics
      12. 5.7.12 EMIF16 Peripheral
        1. 5.7.12.1 EMIF16 Electrical Data/Timing
          1. Table 5-17 EMIF16 Asynchronous Memory Timing Requirements
      13. 5.7.13 MDIO Timing
        1. Table 5-18 MDIO Timing Requirements
        2. Table 5-19 MDIO Switching Characteristics
      14. 5.7.14 Timers Electrical Data/Timing
        1. Table 5-20 Timer Input Timing Requirements
        2. Table 5-21 Timer Output Switching Characteristics
      15. 5.7.15 General-Purpose Input/Output (GPIO)
        1. 5.7.15.1 GPIO Device-Specific Information
        2. 5.7.15.2 GPIO Electrical Data/Timing
          1. Table 5-22 GPIO Input Timing Requirements
          2. Table 5-23 GPIO Output Switching Characteristics
      16. 5.7.16 McBSP Electrical Data/Timing
        1. 5.7.16.1 McBSP Timing
          1. Table 5-24 McBSP Timing Requirements
          2. Table 5-25 McBSP Switching Characteristics
          3. Table 5-26 McBSP Timing Requirements for FSR When GSYNC = 1
      17. 5.7.17 uPP Timing and Switching
        1. Table 5-27 uPP Timing Requirements
        2. Table 5-28 uPP Switching Characteristics
      18. 5.7.18 Trace Electrical Data/Timing
        1. Table 5-29 DSP Trace Switching Characteristics
        2. Table 5-30 STM Trace Switching Characteristics
      19. 5.7.19 JTAG Electrical Data/Timing
        1. Table 5-31 JTAG Test Port Timing Requirements
        2. Table 5-32 JTAG Test Port Switching Characteristics
  6. 6 Detailed Description
    1. 6.1  Recommended Clock and Control Signal Transition Behavior
    2. 6.2  Power Supplies
      1. 6.2.1 Power Supply to Peripheral I/O Mapping
      2. 6.2.2 Power-Supply Sequencing
        1. 6.2.2.1 Core-Before-IO Power Sequencing
        2. 6.2.2.2 IO-Before-Core Power Sequencing
        3. 6.2.2.3 Prolonged Resets
        4. 6.2.2.4 Clocking During Power Sequencing
      3. 6.2.3 Power-Down Sequence
      4. 6.2.4 Power Supply Decoupling and Bulk Capacitors
    3. 6.3  Power Sleep Controller (PSC)
      1. 6.3.1 Power Domains
      2. 6.3.2 Clock Domains
      3. 6.3.3 PSC Register Memory Map
    4. 6.4  Reset Controller
      1. 6.4.1 Power-on Reset
      2. 6.4.2 Hard Reset
      3. 6.4.3 Soft Reset
      4. 6.4.4 Local Reset
      5. 6.4.5 Reset Priority
      6. 6.4.6 Reset Controller Register
    5. 6.5  Main PLL and PLL Controller
      1. 6.5.1 Main PLL Controller Device-Specific Information
        1. 6.5.1.1 Internal Clocks and Maximum Operating Frequencies
        2. 6.5.1.2 Main PLL Controller Operating Modes
      2. 6.5.2 PLL Controller Memory Map
        1. 6.5.2.1 PLL Secondary Control Register (SECCTL)
          1. Table 6-10 PLL Secondary Control Register (SECCTL) Field Descriptions
        2. 6.5.2.2 PLL Controller Divider Register (PLLDIV2, PLLDIV5, PLLDIV8)
          1. Table 6-11 PLL Controller Divider Register (PLLDIVn) Field Descriptions
        3. 6.5.2.3 PLL Controller Clock Align Control Register (ALNCTL)
          1. Table 6-12 PLL Controller Clock Align Control Register (ALNCTL) Field Descriptions
        4. 6.5.2.4 PLLDIV Divider Ratio Change Status Register (DCHANGE)
          1. Table 6-13 PLLDIV Divider Ratio Change Status Register (DCHANGE) Field Descriptions
        5. 6.5.2.5 SYSCLK Status Register (SYSTAT)
          1. Table 6-14 SYSCLK Status Register (SYSTAT) Field Descriptions
        6. 6.5.2.6 Reset Type Status Register (RSTYPE)
          1. Table 6-15 Reset Type Status Register (RSTYPE) Field Descriptions
        7. 6.5.2.7 Reset Control Register (RSTCTRL)
          1. Table 6-16 Reset Control Register (RSTCTRL) Field Descriptions
        8. 6.5.2.8 Reset Configuration Register (RSTCFG)
          1. Table 6-17 Reset Configuration Register (RSTCFG) Field Descriptions
        9. 6.5.2.9 Reset Isolation Register (RSISO)
          1. Table 6-18 Reset Isolation Register (RSISO) Field Descriptions
      3. 6.5.3 Main PLL Control Register
        1. Table 6-19 Main PLL Control Register 0 (MAINPLLCTL0) Field Descriptions
        2. Table 6-20 Main PLL Control Register 1 (MAINPLLCTL1) Field Descriptions
      4. 6.5.4 Main PLL and PLL Controller Initialization Sequence
    6. 6.6  DDR3 PLL
      1. 6.6.1 DDR3 PLL Control Register
        1. Table 6-21 DDR3 PLL Control Register 0 Field Descriptions
        2. Table 6-22 DDR3 PLL Control Register 1 Field Descriptions
      2. 6.6.2 DDR3 PLL Device-Specific Information
      3. 6.6.3 DDR3 PLL Initialization Sequence
    7. 6.7  Enhanced Direct Memory Access (EDMA3) Controller
      1. 6.7.1 EDMA3 Device-Specific Information
      2. 6.7.2 EDMA3 Channel Controller Configuration
      3. 6.7.3 EDMA3 Transfer Controller Configuration
      4. 6.7.4 EDMA3 Channel Synchronization Events
    8. 6.8  Interrupts
      1. 6.8.1 Interrupt Sources and Interrupt Controller
      2. 6.8.2 CIC Registers
        1. 6.8.2.1 CIC0 Register Map
        2. 6.8.2.2 CIC1 Register Map
        3. 6.8.2.3 CIC2 Register Map
      3. 6.8.3 Interprocessor Register Map
      4. 6.8.4 NMI and LRESET
    9. 6.9  Memory Protection Unit (MPU)
      1. 6.9.1 MPU Registers
        1. 6.9.1.1 MPU Register Map
        2. 6.9.1.2 Device-Specific MPU Registers
          1. 6.9.1.2.1 Configuration Register (CONFIG)
            1. Table 6-44 Configuration Register (CONFIG) Field Descriptions
      2. 6.9.2 MPU Programmable Range Registers
        1. 6.9.2.1 Programmable Range n Start Address Register (PROGn_MPSAR)
          1. Table 6-45 Programmable Range n Start Address Register (PROGn_MPSAR) Field Descriptions
        2. 6.9.2.2 Programmable Range n End Address Register (PROGn_MPEAR)
          1. Table 6-46 Programmable Range n End Address Register (PROGn_MPEAR) Field Descriptions
        3. 6.9.2.3 Programmable Range n Memory Protection Page Attribute Register (PROGn_MPPA)
          1. Table 6-47 Programmable Range n Memory Protection Page Attribute Register (PROGn_MPPA) Field Descriptions
        4. 6.9.2.4 MPU Registers Reset Values
    10. 6.10 DDR3 Memory Controller
      1. 6.10.1 DDR3 Memory Controller Device-Specific Information
    11. 6.11 I2C Peripheral
      1. 6.11.1 I2C Device-Specific Information
      2. 6.11.2 I2C Peripheral Register Description(s)
    12. 6.12 HyperLink Peripheral
      1. 6.12.1 HyperLink Device-Specific Interrupt Event
    13. 6.13 PCIe Peripheral
    14. 6.14 Ethernet Media Access Controller (EMAC)
      1. 6.14.1 EMAC Device-Specific Information
      2. 6.14.2 EMAC Peripheral Register Description(s)
      3. 6.14.3 EMAC Electrical Data/Timing (SGMII)
    15. 6.15 Management Data Input/Output (MDIO)
      1. 6.15.1 MDIO Peripheral Registers
    16. 6.16 Timers
      1. 6.16.1 Timers Device-Specific Information
    17. 6.17 Semaphore2
    18. 6.18 Multichannel Buffered Serial Port (McBSP)
      1. 6.18.1 McBSP Peripheral Register
    19. 6.19 Universal Parallel Port (uPP)
      1. 6.19.1 uPP Register Descriptions
    20. 6.20 Serial RapidIO (SRIO) Port
    21. 6.21 Turbo Decoder Coprocessor (TCP3d)
    22. 6.22 Enhanced Viterbi-Decoder Coprocessor (VCP2)
    23. 6.23 Emulation Features and Capability
      1. 6.23.1 Advanced Event Triggering (AET)
      2. 6.23.2 Trace
      3. 6.23.3 IEEE 1149.1 JTAG
        1. 6.23.3.1 IEEE 1149.1 JTAG Compatibility Statement
    24. 6.24 DSP Core Description
    25. 6.25 Memory Map Summary
    26. 6.26 Boot Sequence
    27. 6.27 Boot Modes Supported and PLL Settings
      1. 6.27.1 Boot Device Field
        1. Table 6-64 Boot Mode Pins: Boot Device Values
      2. 6.27.2 Device Configuration Field
        1. 6.27.2.1 EMIF16 / UART / No Boot Device Configuration
          1. Table 6-65 EMIF16 / UART / No Boot Configuration Field Descriptions
          2. 6.27.2.1.1 No Boot Mode
            1. Table 6-66 No Boot Configuration Field Descriptions
          3. 6.27.2.1.2 UART Boot Mode
            1. Table 6-67 UART Boot Configuration Field Descriptions
          4. 6.27.2.1.3 EMIF16 Boot Mode
            1. Table 6-68 EMIF16 Boot Configuration Field Descriptions
        2. 6.27.2.2 Serial Rapid I/O Boot Device Configuration
          1. Table 6-69 Serial Rapid I/O Configuration Field Descriptions
        3. 6.27.2.3 Ethernet (SGMII) Boot Device Configuration
          1. Table 6-70 Ethernet (SGMII) Configuration Field Descriptions
        4. 6.27.2.4 NAND Boot Device Configuration
          1. Table 6-71 NAND Configuration Field Descriptions
        5. 6.27.2.5 PCI Boot Device Configuration
          1. Table 6-72 PCI Device Configuration Field Descriptions
        6. 6.27.2.6 I2C Boot Device Configuration
          1. 6.27.2.6.1 I2C Master Mode
            1. Table 6-74 I2C Master Mode Device Configuration Field Descriptions
          2. 6.27.2.6.2 I2C Passive Mode
            1. Table 6-75 I2C Passive Mode Device Configuration Field Descriptions
        7. 6.27.2.7 SPI Boot Device Configuration
          1. Table 6-76 SPI Device Configuration Field Descriptions
        8. 6.27.2.8 HyperLink Boot Device Configuration
          1. Table 6-77 HyperLink Boot Device Configuration Field Descriptions
      3. 6.27.3 Boot Parameter Table
        1. Table 6-80 PLL Configuration Field Description
        2. 6.27.3.1   Sleep / XIP Mode Parameter Table
          1. Table 6-82 EMIF16 XIP Option Field Descriptions
        3. 6.27.3.2   SRIO Mode Boot Parameter Table
          1. Table 6-84 SRIO Boot Options Description
        4. 6.27.3.3   Ethernet Mode Boot Parameter Table
          1. Table 6-87 Ethernet Options Field Descriptions
          2. Table 6-88 SGMII Config Field Descriptions
        5. 6.27.3.4   NAND Mode Boot Parameter Table
          1. Table 6-90 NAND Boot Parameter Options Bit Field Descriptions
        6. 6.27.3.5   PCIE Mode Boot Parameter Table
          1. Table 6-92 PCIe Options Field Descriptions
        7. 6.27.3.6   I2C Mode Boot Parameter Table
          1. Table 6-94 Register Description
        8. 6.27.3.7   SPI Mode Boot Parameter Table
          1. Table 6-96 SPI Options Field Description
        9. 6.27.3.8   Hyperlink Mode Boot Parameter Table
          1. Table 6-98 Hyperlink Options Field Descriptions
        10. 6.27.3.9   UART Mode Boot Parameter Table
    28. 6.28 PLL Boot Configuration Settings
    29. 6.29 Second-Level Bootloaders
  7. 7 C66x CorePac
    1. 7.1 Memory Architecture
      1. 7.1.1 L1P Memory
      2. 7.1.2 L1D Memory
      3. 7.1.3 L2 Memory
      4. 7.1.4 MSM SRAM
      5. 7.1.5 L3 Memory
    2. 7.2 Memory Protection
    3. 7.3 Bandwidth Management
    4. 7.4 Power-Down Control
    5. 7.5 C66x CorePac Revision
      1. Table 7-2 CorePac Revision ID Register (MM_REVID) Field Descriptions
    6. 7.6 C66x CorePac Register Descriptions
  8. 8 Device Configuration
    1. 8.1 Device Configuration at Device Reset
    2. 8.2 Peripheral Selection After Device Reset
    3. 8.3 Device State Control Registers
      1. 8.3.1  Device Status Register
        1. Table 8-3 Device Status Register Field Descriptions
      2. 8.3.2  Device Configuration Register
        1. Table 8-4 Device Configuration Register Field Descriptions
      3. 8.3.3  JTAG ID (JTAGID) Register Description
        1. Table 8-5 JTAG ID Register Field Descriptions
      4. 8.3.4  Kicker Mechanism (KICK0 and KICK1) Register
      5. 8.3.5  LRESETNMI PIN Status (LRSTNMIPINSTAT) Register
        1. Table 8-6 LRESETNMI PIN Status Register (LRSTNMIPINSTAT) Field Descriptions
      6. 8.3.6  LRESETNMI PIN Status Clear (LRSTNMIPINSTAT_CLR) Register
        1. Table 8-7 LRESETNMI PIN Status Clear Register (LRSTNMIPINSTAT_CLR) Field Descriptions
      7. 8.3.7  Reset Status (RESET_STAT) Register
        1. Table 8-8 Reset Status Register (RESET_STAT) Field Descriptions
      8. 8.3.8  Reset Status Clear (RESET_STAT_CLR) Register
        1. Table 8-9 Reset Status Clear Register (RESET_STAT_CLR) Field Descriptions
      9. 8.3.9  Boot Complete (BOOTCOMPLETE) Register
        1. Table 8-10 Boot Complete Register (BOOTCOMPLETE) Field Descriptions
      10. 8.3.10 Power State Control (PWRSTATECTL) Register
        1. Table 8-11 Power State Control Register (PWRSTATECTL) Field Descriptions
      11. 8.3.11 NMI Event Generation to CorePac (NMIGRx) Register
        1. Table 8-12 NMI Generation Register (NMIGRx) Field Descriptions
      12. 8.3.12 IPC Generation (IPCGRx) Registers
        1. Table 8-13 IPC Generation Registers (IPCGRx) Field Descriptions
      13. 8.3.13 IPC Acknowledgement (IPCARx) Registers
        1. Table 8-14 IPC Acknowledgement Registers (IPCARx) Field Descriptions
      14. 8.3.14 IPC Generation Host (IPCGRH) Register
        1. Table 8-15 IPC Generation Registers (IPCGRH) Field Descriptions
      15. 8.3.15 IPC Acknowledgement Host (IPCARH) Register
        1. Table 8-16 IPC Acknowledgement Register (IPCARH) Field Descriptions
      16. 8.3.16 Timer Input Selection Register (TINPSEL)
        1. Table 8-17 Timer Input Selection Field Description (TINPSEL)
      17. 8.3.17 Timer Output Selection Register (TOUTPSEL)
        1. Table 8-18 Timer Output Selection Field Description (TOUTPSEL)
      18. 8.3.18 Reset Mux (RSTMUXx) Register
        1. Table 8-19 Reset Mux Register Field Descriptions
      19. 8.3.19 Device Speed (DEVSPEED) Register
        1. Table 8-20 Device Speed Register Field Descriptions
      20. 8.3.20 Pin Control 0 (PIN_CONTROL_0) Register
        1. Table 8-21 Pin Control 0 Register Field Descriptions
      21. 8.3.21 Pin Control 1 (PIN_CONTROL_1) Register
        1. Table 8-22 Pin Control 1 Register Field Descriptions
      22. 8.3.22 uPP Clock Source (UPP_CLOCK) Register
        1. Table 8-23 uPP Clock Source Register Field Descriptions
    4. 8.4 Pullup and Pulldown Resistors
  9. 9 System Interconnect
    1. 9.1 Internal Buses and Switch Fabrics
    2. 9.2 Switch Fabric Connections Matrix
    3. 9.3 TeraNet Switch Fabric Connections
    4. 9.4 Bus Priorities
      1. 9.4.1 Packet DMA Priority Allocation (PKTDMA_PRI_ALLOC) Register
        1. Table 9-3 Packet DMA Priority Allocation Register (PKTDMA_PRI_ALLOC) Field Descriptions
      2. 9.4.2 EMAC / uPP Priority Allocation (EMAC_UPP_PRI_ALLOC) Register
        1. Table 9-4 EMAC / uPP Priority Allocation Register (EMAC_UPP_PRI_ALLOC) Field Descriptions
  10. 10Device and Documentation Support
    1. 10.1 Device Nomenclature
    2. 10.2 Tools and Software
    3. 10.3 Documentation Support
    4. 10.4 Related Links
    5. 10.5 Support Resources
    6. 10.6 Trademarks
    7. 10.7 Electrostatic Discharge Caution
    8. 10.8 Glossary
  11. 11Mechanical Packaging and Orderable Information
    1. 11.1 Packaging Information

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • CZH|625
  • GZH|625
サーマルパッド・メカニカル・データ
発注情報

6.14.2 EMAC Peripheral Register Description(s)

The memory maps of the EMAC are shown in Table 6-55 through Table 6-60.

Table 6-55 Ethernet MAC (EMAC) Control Registers

HEX ADDRESS ACRONYM REGISTER NAME
02C0 8000 TXIDVER Transmit Identification and Version Register
02C0 8004 TXCONTROL Transmit Control Register
02C0 8008 TXTEARDOWN Transmit Teardown register
02C0 800F - Reserved
02C0 8010 RXIDVER Receive Identification and Version Register
02C0 8014 RXCONTROL Receive Control Register
02C0 8018 RXTEARDOWN Receive Teardown Register
02C0 801C - Reserved
02C0 8020 - 02C0 807C - Reserved
02C0 8080 TXINTSTATRAW Transmit Interrupt Status (Unmasked) Register
02C0 8084 TXINTSTATMASKED Transmit Interrupt Status (Masked) Register
02C0 8088 TXINTMASKSET Transmit Interrupt Mask Set Register
02C0 808C TXINTMASKCLEAR Transmit Interrupt Mask Clear Register
02C0 8090 MACINVECTOR MAC Input Vector Register
02C0 8094 MACEOIVECTOR MAC End of Interrupt Vector Register
02C0 8098 - 02C0 819C - Reserved
02C0 80A0 RXINTSTATRAW Receive Interrupt Status (Unmasked) Register
02C0 80A4 RXINTSTATMASKED Receive Interrupt Status (Masked) Register
02C0 80A8 RXINTMASKSET Receive Interrupt Mask Set Register
02C0 80AC RXINTMASKCLEAR Receive Interrupt Mask Clear Register
02C0 80B0 MACINTSTATRAW MAC Interrupt Status (Unmasked) Register
02C0 80B4 MACINTSTATMASKED MAC Interrupt Status (Masked) Register
02C0 80B8 MACINTMASKSET MAC Interrupt Mask Set Register
02C0 80BC MACINTMASKCLEAR MAC Interrupt Mask Clear Register
02C0 80C0 - 02C0 80FC - Reserved
02C0 8100 RXMBPENABLE Receive Multicast/Broadcast/Promiscuous Channel Enable Register
02C0 8104 RXUNICASTSET Receive Unicast Enable Set Register
02C0 8108 RXUNICASTCLEAR Receive Unicast Clear Register
02C0 810C RXMAXLEN Receive Maximum Length Register
02C0 8110 RXBUFFEROFFSET Receive Buffer Offset Register
02C0 8114 RXFILTERLOWTHRESH Receive Filter Low Priority Frame Threshold Register
02C0 8118 - 02C0 811C - Reserved
02C0 8120 RX0FLOWTHRESH Receive Channel 0 Flow Control Threshold Register
02C0 8124 RX1FLOWTHRESH Receive Channel 1 Flow Control Threshold Register
02C0 8128 RX2FLOWTHRESH Receive Channel 2 Flow Control Threshold Register
02C0 812C RX3FLOWTHRESH Receive Channel 3 Flow Control Threshold Register
02C0 8130 RX4FLOWTHRESH Receive Channel 4 Flow Control Threshold Register
02C0 8134 RX5FLOWTHRESH Receive Channel 5 Flow Control Threshold Register
02C0 8138 RX6FLOWTHRESH Receive Channel 6 Flow Control Threshold Register
02C0 813C RX7FLOWTHRESH Receive Channel 7 Flow Control Threshold Register
02C0 8140 RX0FREEBUFFER Receive Channel 0 Free Buffer Count Register
02C0 8144 RX1FREEBUFFER Receive Channel 1 Free Buffer Count Register
02C0 8148 RX2FREEBUFFER Receive Channel 2 Free Buffer Count Register
02C0 814C RX3FREEBUFFER Receive Channel 3 Free Buffer Count Register
02C0 8150 RX4FREEBUFFER Receive Channel 4 Free Buffer Count Register
02C0 8154 RX5FREEBUFFER Receive Channel 5 Free Buffer Count Register
02C0 8158 RX6FREEBUFFER Receive Channel 6 Free Buffer Count Register
02C0 815C RX7FREEBUFFER Receive Channel 7 Free Buffer Count Register
02C0 8160 MACCONTROL MAC Control Register
02C0 8164 MACSTATUS MAC Status Register
02C0 8168 EMCONTROL Emulation Control Register
02C0 816C FIFOCONTROL FIFO Control Register
02C0 8170 MACCONFIG MAC Configuration Register
02C0 8174 SOFTRESET Soft Reset Register
02C0 81D0 MACSRCADDRLO MAC Source Address Low Bytes Register
02C0 81D4 MACSRCADDRHI MAC Source Address High Bytes Register
02C0 81D8 MACHASH1 MAC Hash Address Register 1
02C0 81DC MACHASH2 MAC Hash Address Register 2
02C0 81E0 BOFFTEST Back Off Test Register
02C0 81E4 TPACETEST Transmit Pacing Algorithm Test Register
02C0 81E8 RXPAUSE Receive Pause Timer Register
02C0 81EC TXPAUSE Transmit Pause Timer Register
02C0 8200 - 02C0 82FC - See Table 6-56.
02C0 8300 - 02C0 84FC - Reserved
02C0 8500 MACADDRLO MAC Address Low Bytes Register (used in Receive Address Matching)
02C0 8504 MACADDRHI MAC Address High Bytes Register (used in Receive Address Matching)
02C0 8508 MACINDEX MAC Index Register
02C0 850C - 02C0 85FC - Reserved
02C0 8600 TX0HDP Transmit Channel 0 DMA Head Descriptor Pointer Register
02C0 8604 TX1HDP Transmit Channel 1 DMA Head Descriptor Pointer Register
02C0 8608 TX2HDP Transmit Channel 2 DMA Head Descriptor Pointer Register
02C0 860C TX3HDP Transmit Channel 3 DMA Head Descriptor Pointer Register
02C0 8610 TX4HDP Transmit Channel 4 DMA Head Descriptor Pointer Register
02C0 8614 TX5HDP Transmit Channel 5 DMA Head Descriptor Pointer Register
02C0 8618 TX6HDP Transmit Channel 6 DMA Head Descriptor Pointer Register
02C0 861C TX7HDP Transmit Channel 7 DMA Head Descriptor Pointer Register
02C0 8620 RX0HDP Receive Channel 0 DMA Head Descriptor Pointer Register
02C0 8624 RX1HDP Receive t Channel 1 DMA Head Descriptor Pointer Register
02C0 8628 RX2HDP Receive Channel 2 DMA Head Descriptor Pointer Register
02C0 862C RX3HDP Receive t Channel 3 DMA Head Descriptor Pointer Register
02C0 8630 RX4HDP Receive Channel 4 DMA Head Descriptor Pointer Register
02C0 8634 RX5HDP Receive t Channel 5 DMA Head Descriptor Pointer Register
02C0 8638 RX6HDP Receive Channel 6 DMA Head Descriptor Pointer Register
02C0 863C RX7HDP Receive t Channel 7 DMA Head Descriptor Pointer Register
02C0 8640 TX0CP Transmit Channel 0 Completion Pointer (Interrupt Acknowledge) Register
02C0 8644 TX1CP Transmit Channel 1 Completion Pointer (Interrupt Acknowledge) Register
02C0 8648 TX2CP Transmit Channel 2 Completion Pointer (Interrupt Acknowledge) Register
02C0 864C TX3CP Transmit Channel 3 Completion Pointer (Interrupt Acknowledge) Register
02C0 8650 TX4CP Transmit Channel 4 Completion Pointer (Interrupt Acknowledge) Register
02C0 8654 TX5CP Transmit Channel 5 Completion Pointer (Interrupt Acknowledge) Register
02C0 8658 TX6CP Transmit Channel 6 Completion Pointer (Interrupt Acknowledge) Register
02C0 865C TX7CP Transmit Channel 7 Completion Pointer (Interrupt Acknowledge) Register
02C0 8660 RX0CP Receive Channel 0 Completion Pointer (Interrupt Acknowledge) Register
02C0 8664 RX1CP Receive Channel 1 Completion Pointer (Interrupt Acknowledge) Register
02C0 8668 RX2CP Receive Channel 2 Completion Pointer (Interrupt Acknowledge) Register
02C0 866C RX3CP Receive Channel 3 Completion Pointer (Interrupt Acknowledge) Register
02C0 8670 RX4CP Receive Channel 4 Completion Pointer (Interrupt Acknowledge) Register
02C0 8674 RX5CP Receive Channel 5 Completion Pointer (Interrupt Acknowledge) Register
02C0 8678 RX6CP Receive Channel 6 Completion Pointer (Interrupt Acknowledge) Register
02C0 867C RX7CP Receive Channel 7 Completion Pointer (Interrupt Acknowledge) Register
02C0 8680 - 02C0 86FC - Reserved
02C0 8700 - 02C0 877C - Reserved
02C0 8780 - 02C0 8FFF - Reserved

Table 6-56 EMAC Statistics Registers

HEX ADDRESS ACRONYM REGISTER NAME
02C0 8200 RXGOODFRAMES Good Receive Frames Register
02C0 8204 RXBCASTFRAMES Broadcast Receive Frames Register (Total number of Good Broadcast Frames Receive)
02C0 8208 RXMCASTFRAMES Multicast Receive Frames Register (Total number of Good Multicast Frames Received)
02C0 820C RXPAUSEFRAMES Pause Receive Frames Register
02C0 8210 RXCRCERRORS Receive CRC Errors Register (Total number of Frames Received with CRC Errors)
02C0 8214 RXALIGNCODEERRORS Receive Alignment/Code Errors register (Total number of frames received with alignment/code errors)
02C0 8218 RXOVERSIZED Receive Oversized Frames Register (Total number of Oversized Frames Received)
02C0 821C RXJABBER Receive Jabber Frames Register (Total number of Jabber Frames Received)
02C0 8220 RXUNDERSIZED Receive Undersized Frames Register (Total number of Undersized Frames Received)
02C0 8224 RXFRAGMENTS Receive Frame Fragments Register
02C0 8228 RXFILTERED Filtered Receive Frames Register
02C0 822C RXQOSFILTERERED Received QOS Filtered Frames Register
02C0 8230 RXOCTETS Receive Octet Frames Register (Total number of Received Bytes in Good Frames)
02C0 8234 TXGOODFRAMES Good Transmit Frames Register (Total number of Good Frames Transmitted)
02C0 8238 TXBCASTFRAMES Broadcast Transmit Frames Register
02C0 823C TXMCASTFRAMES Multicast Transmit Frames Register
02C0 8240 TXPAUSEFRAMES Pause Transmit Frames Register
02C0 8244 TXDEFERED Deferred Transmit Frames Register
02C0 8248 TXCOLLISION Transmit Collision Frames Register
02C0 824C TXSINGLECOLL Transmit Single Collision Frames Register
02C0 8250 TXMULTICOLL Transmit Multiple Collision Frames Register
02C0 8254 TXEXCESSIVECOLL Transmit Excessive Collision Frames Register
02C0 8258 TXLATECOLL Transmit Late Collision Frames Register
02C0 825C TXUNDERRUN Transmit Under Run Error Register
02C0 8260 TXCARRIERSENSE Transmit Carrier Sense Errors Register
02C0 8264 TXOCTETS Transmit Octet Frames Register
02C0 8268 FRAME64 Transmit and Receive 64 Octet Frames Register
02C0 826C FRAME65T127 Transmit and Receive 65 to 127 Octet Frames Register
02C0 8270 FRAME128T255 Transmit and Receive 128 to 255 Octet Frames Register
02C0 8274 FRAME256T511 Transmit and Receive 256 to 511 Octet Frames Register
02C0 8278 FRAME512T1023 Transmit and Receive 512 to 1023 Octet Frames Register
02C0 827C FRAME1024TUP Transmit and Receive 1024 to 1518 Octet Frames Register
02C0 8280 NETOCTETS Network Octet Frames Register
02C0 8284 RXSOFOVERRUNS Receive FIFO or DMA Start of Frame Overruns Register
02C0 8288 RXMOFOVERRUNS Receive FIFO or DMA Middle of Frame Overruns Register
02C0 828C RXDMAOVERRUNS Receive DMA Start of Frame and Middle of Frame Overruns Register
02C0 8290 - 02C0 82FC - Reserved

Table 6-57 EMAC Descriptor Memory

HEX ADDRESS ACRONYM REGISTER NAME
02C0 A000 - 02C0 BFFF - EMAC Descriptor Memory

Table 6-58 SGMII Control Registers

HEX ADDRESS ACRONYM REGISTER NAME
02C0 8900 IDVER Identification and Version register
02C0 8904 SOFT_RESET Software Reset Register
02C0 8910 CONTROL Control Register
02C0 8914 STATUS Status Register
02C0 8918 MR_ADV_ABILITY Advertised Ability Register
02C0 891C - Reserved
02C0 8920 MR_LP_ADV_ABILITY Link Partner Advertised Ability Register
02C0 8924 - 02C0 8948 - Reserved

Table 6-59 EMIC Control Registers

HEX ADDRESS ACRONYM REGISTER NAME
02C0 8A00 IDVER Identification and Version register
02C0 8A04 SOFT_RESET Software Reset Register
02C0 8A08 EM_CONTROL Emulation Control Register
02C0 8A0C INT_CONTROL Interrupt Control Register
02C0 8A10 C0_RX_THRESH_EN Receive Threshold Interrupt Enable Register for CorePac0
02C0 8A14 C0_RX_EN Receive Interrupt Enable Register for CorePac0
02C0 8A18 C0_TX_EN Transmit Interrupt Enable Register for CorePac0
02C0 8A1C C0_MISC_EN Misc Interrupt Enable Register for CorePac0
02C0 8A10 C1_RX_THRESH_EN Receive Threshold Interrupt Enable Register for CorePac1 (C6657 only)
02C0 8A14 C1_RX_EN Receive Interrupt Enable Register for CorePac1 (C6657 only)
02C0 8A18 C1_TX_EN Transmit Interrupt Enable Register for CorePac1 (C6657 only)
02C0 8A1C C1_MISC_EN Misc Interrupt Enable Register for CorePac1 (C6657 only)
02C0 8A90 C0_RX_THRESH_STAT Receive Threshold Masked Interrupt Status Register for CorePac0
02C0 8A94 C0_RX_STAT Receive Interrupt Masked Interrupt Status Register for CorePac0
02C0 8A98 C0_TX_STAT Transmit Interrupt Masked Interrupt Status Register for CorePac0
02C0 8A9C C0_MISC_STAT Misc Interrupt Masked Interrupt Status Register for CorePac0
02C0 8AA0 C1_RX_THRESH_STAT Receive Threshold Masked Interrupt Status Register for CorePac1 (C6657 only)
02C0 8AA4 C1_RX_STAT Receive Interrupt Masked Interrupt Status Register for CorePac1 (C6657 only)
02C0 8AA8 C1_TX_STAT Transmit Interrupt Masked Interrupt Status Register for CorePac1 (C6657 only)
02C0 8AAC C1_MISC_STAT Misc Interrupt Masked Interrupt Status Register for CorePac1 (C6657 only)
02C0 8B10 C0_RX_IMAX Receive Interrupts Per Millisecond for CorePac0
02C0 8B14 C0_TX_IMAX Transmit Interrupts Per Millisecond for CorePac0
02C0 8B18 C1_RX_IMAX Receive Interrupts Per Millisecond for CorePac1 (C6657 only)
02C0 8B1C C1_TX_IMAX Transmit Interrupts Per Millisecond for CorePac1 (C6657 only)