JAJSDV7F June   2009  – January 2017 TMS320C6742

PRODUCTION DATA.  

  1. 1デバイスの概要
    1. 1.1 特長
    2. 1.2 アプリケーション
    3. 1.3 概要
    4. 1.4 機能ブロック図
  2. 2Revision History
  3. 3Device Comparison
    1. 3.1 Device Characteristics
    2. 3.2 Device Compatibility
    3. 3.3 DSP Subsystem
      1. 3.3.1 C674x DSP CPU Description
      2. 3.3.2 DSP Memory Mapping
        1. 3.3.2.1 External Memories
        2. 3.3.2.2 DSP Internal Memories
        3. 3.3.2.3 C674x CPU
    4. 3.4 Memory Map Summary
      1. Table 3-4 C6742 Top Level Memory Map
    5. 3.5 Pin Assignments
      1. 3.5.1 Pin Map (Bottom View)
    6. 3.6 Pin Multiplexing Control
    7. 3.7 Terminal Functions
      1. 3.7.1  Device Reset, NMI and JTAG
      2. 3.7.2  High-Frequency Oscillator and PLL
      3. 3.7.3  Real-Time Clock and 32-kHz Oscillator
      4. 3.7.4  DEEPSLEEP Power Control
      5. 3.7.5  External Memory Interface A (EMIFA)
      6. 3.7.6  DDR2/mDDR Controller
      7. 3.7.7  Serial Peripheral Interface Modules (SPI)
      8. 3.7.8  Enhanced Capture/Auxiliary PWM Modules (eCAP0)
      9. 3.7.9  Enhanced Pulse Width Modulators (eHRPWM)
      10. 3.7.10 Boot
      11. 3.7.11 Universal Asynchronous Receiver/Transmitters (UART0)
      12. 3.7.12 Inter-Integrated Circuit Modules(I2C0)
      13. 3.7.13 Timers
      14. 3.7.14 Multichannel Audio Serial Ports (McASP)
      15. 3.7.15 Multichannel Buffered Serial Ports (McBSP)
      16. 3.7.16 Universal Host-Port Interface (UHPI)
      17. 3.7.17 General Purpose Input Output
      18. 3.7.18 Reserved and No Connect
      19. 3.7.19 Supply and Ground
    8. 3.8 Unused Pin Configurations
  4. 4Device Configuration
    1. 4.1 Boot Modes
    2. 4.2 SYSCFG Module
    3. 4.3 Pullup/Pulldown Resistors
  5. 5Specifications
    1. 5.1 Absolute Maximum Ratings Over Operating Junction Temperature Range (Unless Otherwise Noted)
    2. 5.2 Handling Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Notes on Recommended Power-On Hours (POH)
    5. 5.5 Electrical Characteristics Over Recommended Ranges of Supply Voltage and Operating Junction Temperature (Unless Otherwise Noted)
  6. 6Peripheral Information and Electrical Specifications
    1. 6.1  Parameter Information
      1. 6.1.1 Parameter Information Device-Specific Information
        1. 6.1.1.1 Signal Transition Levels
    2. 6.2  Recommended Clock and Control Signal Transition Behavior
    3. 6.3  Power Supplies
      1. 6.3.1 Power-On Sequence
      2. 6.3.2 Power-Off Sequence
    4. 6.4  Reset
      1. 6.4.1 Power-On Reset (POR)
      2. 6.4.2 Warm Reset
      3. 6.4.3 Reset Electrical Data Timings
    5. 6.5  Crystal Oscillator or External Clock Input
    6. 6.6  Clock PLLs
      1. 6.6.1 PLL Device-Specific Information
      2. 6.6.2 Device Clock Generation
      3. 6.6.3 Dynamic Voltage and Frequency Scaling (DVFS)
    7. 6.7  Interrupts
      1. 6.7.1 DSP Interrupts
    8. 6.8  Power and Sleep Controller (PSC)
      1. 6.8.1 Power Domain and Module Topology
        1. 6.8.1.1 Power Domain States
        2. 6.8.1.2 Module States
    9. 6.9  Enhanced Direct Memory Access Controller (EDMA3)
      1. 6.9.1 EDMA3 Channel Synchronization Events
      2. 6.9.2 EDMA3 Peripheral Register Descriptions
    10. 6.10 External Memory Interface A (EMIFA)
      1. 6.10.1 EMIFA Asynchronous Memory Support
      2. 6.10.2 EMIFA Synchronous DRAM Memory Support
      3. 6.10.3 EMIFA SDRAM Loading Limitations
      4. 6.10.4 EMIFA Connection Examples
      5. 6.10.5 External Memory Interface Register Descriptions
      6. 6.10.6 EMIFA Electrical Data/Timing
        1. Table 6-19 Timing Requirements for EMIFA SDRAM Interface
        2. Table 6-20 Switching Characteristics for EMIFA SDRAM Interface
        3. Table 6-21 Timing Requirements for EMIFA Asynchronous Memory Interface
    11. 6.11 DDR2/mDDR Memory Controller
      1. 6.11.1 DDR2/mDDR Memory Controller Electrical Data/Timing
      2. 6.11.2 DDR2/mDDR Memory Controller Register Description(s)
      3. 6.11.3 DDR2/mDDR Interface
        1. 6.11.3.1  DDR2/mDDR Interface Schematic
        2. 6.11.3.2  Compatible JEDEC DDR2/mDDR Devices
        3. 6.11.3.3  PCB Stackup
        4. 6.11.3.4  Placement
        5. 6.11.3.5  DDR2/mDDR Keep Out Region
        6. 6.11.3.6  Bulk Bypass Capacitors
        7. 6.11.3.7  High-Speed Bypass Capacitors
        8. 6.11.3.8  Net Classes
        9. 6.11.3.9  DDR2/mDDR Signal Termination
        10. 6.11.3.10 VREF Routing
        11. 6.11.3.11 DDR2/mDDR CK and ADDR_CTRL Routing
        12. 6.11.3.12 DDR2/mDDR Boundary Scan Limitations
    12. 6.12 Memory Protection Units
    13. 6.13 Multichannel Audio Serial Port (McASP)
      1. 6.13.1 McASP Peripheral Registers Description(s)
      2. 6.13.2 McASP Electrical Data/Timing
        1. 6.13.2.1 Multichannel Audio Serial Port 0 (McASP0) Timing
          1. Table 6-42 Timing Requirements for McASP0 (1.2V, 1.1V)
          2. Table 6-43 Timing Requirements for McASP0 (1.0V)
          3. Table 6-44 Switching Characteristics for McASP0 (1.2V, 1.1V)
          4. Table 6-45 Switching Characteristics for McASP0 (1.0V)
    14. 6.14 Multichannel Buffered Serial Port (McBSP)
      1. 6.14.1 McBSP Peripheral Register Description(s)
      2. 6.14.2 McBSP Electrical Data/Timing
        1. 6.14.2.1 Multichannel Buffered Serial Port (McBSP) Timing
          1. Table 6-47 Timing Requirements for McBSP1 [1.2V, 1.1V] (see )
          2. Table 6-48 Timing Requirements for McBSP1 [1.0V] (see )
          3. Table 6-49 Switching Characteristics for McBSP1 [1.2V, 1.1V] (see )
          4. Table 6-50 Switching Characteristics for McBSP1 [1.0V] (see )
          5. Table 6-51 Timing Requirements for McBSP1 FSR When GSYNC = 1 (see )
    15. 6.15 Serial Peripheral Interface Ports (SPI1)
      1. 6.15.1 SPI Peripheral Registers Description(s)
      2. 6.15.2 SPI Electrical Data/Timing
        1. 6.15.2.1 Serial Peripheral Interface (SPI) Timing
          1. Table 6-53 General Timing Requirements for SPI1 Master Modes
          2. Table 6-54 General Timing Requirements for SPI1 Slave Modes
          3. Table 6-55 Additional SPI1 Master Timings, 4-Pin Enable Option
          4. Table 6-56 Additional SPI1 Master Timings, 4-Pin Chip Select Option
    16. 6.16 Inter-Integrated Circuit Serial Ports (I2C)
      1. 6.16.1 I2C Device-Specific Information
      2. 6.16.2 I2C Peripheral Registers Description(s)
      3. 6.16.3 I2C Electrical Data/Timing
        1. 6.16.3.1 Inter-Integrated Circuit (I2C) Timing
          1. Table 6-62 Timing Requirements for I2C Input
          2. Table 6-63 Switching Characteristics for I2C
    17. 6.17 Universal Asynchronous Receiver/Transmitter (UART)
      1. 6.17.1 UART Peripheral Registers Description(s)
      2. 6.17.2 UART Electrical Data/Timing
        1. Table 6-65 Timing Requirements for UART Receive (see )
        2. Table 6-66 Switching Characteristics Over Recommended Operating Conditions for UARTx Transmit (see )
    18. 6.18 Host-Port Interface (UHPI)
      1. 6.18.1 HPI Device-Specific Information
      2. 6.18.2 HPI Peripheral Register Description(s)
      3. 6.18.3 HPI Electrical Data/Timing
        1. Table 6-68 Timing Requirements for Host-Port Interface [1.2V, 1.1V]
        2. Table 6-69 Switching Characteristics Over Recommended Operating Conditions for Host-Port Interface [1.2V, 1.1V]
        3. Table 6-70 Switching Characteristics Over Recommended Operating Conditions for Host-Port Interface [1.0V]
    19. 6.19 Enhanced Capture (eCAP) Peripheral
      1. Table 6-72 Timing Requirements for Enhanced Capture (eCAP)
      2. Table 6-73 Switching Characteristics Over Recommended Operating Conditions for eCAP
    20. 6.20 Enhanced High-Resolution Pulse-Width Modulator (eHRPWM)
      1. 6.20.1 Enhanced Pulse Width Modulator (eHRPWM) Timing
        1. Table 6-75 Timing Requirements for eHRPWM
        2. Table 6-76 Switching Characteristics Over Recommended Operating Conditions for eHRPWM
      2. 6.20.2 Trip-Zone Input Timing
    21. 6.21 Timers
      1. 6.21.1 Timer Electrical Data/Timing
        1. Table 6-79 Timing Requirements for Timer Input (see )
        2. Table 6-80 Switching Characteristics Over Recommended Operating Conditions for Timer Output
    22. 6.22 Real Time Clock (RTC)
      1. 6.22.1 Clock Source
      2. 6.22.2 Real-Time Clock Register Descriptions
    23. 6.23 General-Purpose Input/Output (GPIO)
      1. 6.23.1 GPIO Register Description(s)
      2. 6.23.2 GPIO Peripheral Input/Output Electrical Data/Timing
        1. Table 6-83 Timing Requirements for GPIO Inputs (see )
        2. Table 6-84 Switching Characteristics Over Recommended Operating Conditions for GPIO Outputs (see )
      3. 6.23.3 GPIO Peripheral External Interrupts Electrical Data/Timing
        1. Table 6-85 Timing Requirements for External Interrupts (see )
    24. 6.24 Emulation Logic
      1. 6.24.1 JTAG Port Description
      2. 6.24.2 Scan Chain Configuration Parameters
      3. 6.24.3 Initial Scan Chain Configuration
      4. 6.24.4 IEEE 1149.1 JTAG
        1. 6.24.4.1 JTAG Peripheral Register Description(s) – JTAG ID Register (DEVIDR0)
        2. 6.24.4.2 JTAG Test-Port Electrical Data/Timing
          1. Table 6-91 Timing Requirements for JTAG Test Port (see )
          2. Table 6-92 Switching Characteristics Over Recommended Operating Conditions for JTAG Test Port (see )
      5. 6.24.5 JTAG 1149.1 Boundary Scan Considerations
  7. 7Device and Documentation Support
    1. 7.1 Device Nomenclature
    2. 7.2 Tools and Software
    3. 7.3 Documentation Support
    4. 7.4 Community Resources
    5. 7.5 商標
    6. 7.6 静電気放電に関する注意事項
    7. 7.7 Export Control Notice
    8. 7.8 Glossary
  8. 8Mechanical Packaging and Orderable Information
    1. 8.1 Thermal Data for ZCE Package
    2. 8.2 Thermal Data for ZWT Package
    3. 8.3 Packaging Information

パッケージ・オプション

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メカニカル・データ（パッケージ｜ピン）
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サーマルパッド・メカニカル・データ
発注情報

Table 6-56 Additional(7) SPI1 Master Timings, 4-Pin Chip Select Option(1)(2)

NO. PARAMETER 1.2V 1.1V 1.0V UNIT
MIN MAX MIN MAX MIN MAX
19 td(SCS_SPC)M Delay from SPI1_SCS active to first SPI1_CLK(3)(4) Polarity = 0, Phase = 0,
to SPI1_CLK rising		 2P-1 2P-5 2P-6 ns
Polarity = 0, Phase = 1,
to SPI1_CLK rising		 0.5M+2P-1 0.5M+2P-5 0.5M+2P-6
Polarity = 1, Phase = 0,
to SPI1_CLK falling		 2P-1 2P-5 2P-6
Polarity = 1, Phase = 1,
to SPI1_CLK falling		 0.5M+2P-1 0.5M+2P-5 0.5M+2P-6
20 td(SPC_SCS)M Delay from final SPI1_CLK edge to master deasserting SPI1_SCS(5)(6) Polarity = 0, Phase = 0,
from SPI1_CLK falling		 0.5M+P-1 0.5M+P-5 0.5M+P-6 ns
Polarity = 0, Phase = 1,
from SPI1_CLK falling		 P-1 P-5 P-6
Polarity = 1, Phase = 0,
from SPI1_CLK rising		 0.5M+P-1 0.5M+P-5 0.5M+P-6
Polarity = 1, Phase = 1,
from SPI1_CLK rising		 P-1 P-5 P-6
(1) P = SYSCLK2 period; M = tc(SPC)M (SPI master bit clock period)
(2) Figure shows only Polarity = 0, Phase = 0 as an example. Table gives parameters for all four master clocking modes.
(3) In the case where the master SPI is ready with new data before SPI1_SCS assertion.
(4) This delay can be increased under software control by the register bit field SPIDELAY.C2TDELAY[4:0].
(5) Except for modes when SPIDAT1.CSHOLD is enabled and there is additional data to transmit. In this case, SPI1_SCS will remain asserted.
(6) This delay can be increased under software control by the register bit field SPIDELAY.T2CDELAY[4:0].
(7) These parameters are in addition to the general timings for SPI master modes (Table 6-53).

Table 6-57 Additional(10) SPI1 Master Timings, 5-Pin Option(1)(2)

NO. PARAMETER 1.2V 1.1V 1.0V UNIT
MIN MAX MIN MAX MIN MAX
18 td(SPC_ENA)M Max delay for slave to deassert SPI1_ENA after final SPI1_CLK edge to ensure master does not begin the next transfer.(3) Polarity = 0, Phase = 0,
from SPI1_CLK falling		 0.5M+P+5 0.5M+P+5 0.5M+P+6 ns
Polarity = 0, Phase = 1,
from SPI1_CLK falling		 P+5 P+5 P+6
Polarity = 1, Phase = 0,
from SPI1_CLK rising		 0.5M+P+5 0.5M+P+5 0.5M+P+6
Polarity = 1, Phase = 1,
from SPI1_CLK rising		 P+5 P+5 P+6
20 td(SPC_SCS)M Delay from final SPI1_CLK edge to
master deasserting SPI1_SCS(4)(5) 		Polarity = 0, Phase = 0,
from SPI1_CLK falling		 0.5M+P-1 0.5M+P-5 0.5M+P-6 ns
Polarity = 0, Phase = 1,
from SPI1_CLK falling		 P-1 P-5 P-6
Polarity = 1, Phase = 0,
from SPI1_CLK rising		 0.5M+P-1 0.5M+P-5 0.5M+P-6
Polarity = 1, Phase = 1,
from SPI1_CLK rising		 P-1 P-5 P-6
21 td(SCSL_ENAL)M Max delay for slave SPI to drive SPI1_ENA valid after master asserts SPI1_SCS to delay the
master from beginning the next transfer,		 C2TDELAY+P C2TDELAY+P C2TDELAY+P ns
22 td(SCS_SPC)M Delay from SPI1_SCS active to first SPI1_CLK(6)(7)(8) Polarity = 0, Phase = 0,
to SPI1_CLK rising		 2P-1 2P-5 2P-6 ns
Polarity = 0, Phase = 1,
to SPI1_CLK rising		 0.5M+2P-1 0.5M+2P-5 0.5M+2P-6
Polarity = 1, Phase = 0,
to SPI1_CLK falling		 2P-1 2P-5 2P-6
Polarity = 1, Phase = 1,
to SPI1_CLK falling		 0.5M+2P-1 0.5M+2P-5 0.5M+2P-6
23 td(ENA_SPC)M Delay from assertion of SPI1_ENA low to first SPI1_CLK edge.(9) Polarity = 0, Phase = 0,
to SPI1_CLK rising		 3P+5 3P+5 3P+6 ns
Polarity = 0, Phase = 1,
to SPI1_CLK rising		 0.5M+3P+5 0.5M+3P+5 0.5M+3P+6
Polarity = 1, Phase = 0,
to SPI1_CLK falling		 3P+5 3P+5 3P+6
Polarity = 1, Phase = 1,
to SPI1_CLK falling		 0.5M+3P+5 0.5M+3P+5 0.5M+3P+6
(1) P = SYSCLK2 period; M = tc(SPC)M (SPI master bit clock period)
(2) Figure shows only Polarity = 0, Phase = 0 as an example. Table gives parameters for all four master clocking modes.
(3) In the case where the master SPI is ready with new data before SPI1_ENA deassertion.
(4) Except for modes when SPIDAT1.CSHOLD is enabled and there is additional data to transmit. In this case, SPI1_SCS will remain asserted.
(5) This delay can be increased under software control by the register bit field SPIDELAY.T2CDELAY[4:0].
(6) If SPI1_ENA is asserted immediately such that the transmission is not delayed by SPI1_ENA.
(7) In the case where the master SPI is ready with new data before SPI1_SCS assertion.
(8) This delay can be increased under software control by the register bit field SPIDELAY.C2TDELAY[4:0].
(9) If SPI1_ENA was initially deasserted high and SPI1_CLK is delayed.
(10) These parameters are in addition to the general timings for SPI master modes (Table 6-54).

Table 6-58 Additional(3) SPI1 Slave Timings, 4-Pin Enable Option(1)(2)

NO. PARAMETER 1.2V 1.1V 1.0V UNIT
MIN MAX MIN MAX MIN MAX
24 td(SPC_ENAH)S Delay from final SPI1_CLK edge to slave deasserting SPI1_ENA. Polarity = 0, Phase = 0,
from SPI1_CLK falling		 1.5P-3 2.5P+15 1.5P-10 2.5P+17 1.5P-12 2.5P+19 ns
Polarity = 0, Phase = 1,
from SPI1_CLK falling		 –0.5M+1.5P-3 –0.5M+2.5P+15 –0.5M+1.5P-10 –0.5M+2.5P+17 –0.5M+1.5P-12 –0.5M+2.5P+19
Polarity = 1, Phase = 0,
from SPI1_CLK rising		 1.5P-3 2.5P+15 1.5P-10 2.5P+17 1.5P-12 2.5P+19
Polarity = 1, Phase = 1,
from SPI1_CLK rising		 –0.5M+1.5P-3 –0.5M+2.5P+15 –0.5M+1.5P-10 –0.5M+2.5P+17 –0.5M+1.5P-12 –0.5M+2.5P+19
(1) P = SYSCLK2 period; M = tc(SPC)M (SPI master bit clock period)
(2) Figure shows only Polarity = 0, Phase = 0 as an example. Table gives parameters for all four slave clocking modes.
(3) These parameters are in addition to the general timings for SPI slave modes (Table 6-54).

Table 6-59 Additional(3) SPI1 Slave Timings, 4-Pin Chip Select Option(1)(2)

NO. PARAMETER 1.2V 1.1V 1.0V UNIT
MIN MAX MIN MAX MIN MAX
25 td(SCSL_SPC)S Required delay from SPI1_SCS asserted at slave to first SPI1_CLK edge at slave. P+1.5 P+1.5 P+1.5 ns
26 td(SPC_SCSH)S Required delay from final SPI1_CLK edge before SPI1_SCS is deasserted. Polarity = 0, Phase = 0,
from SPI1_CLK falling		 0.5M+P+4 0.5M+P+5 0.5M+P+6 ns
Polarity = 0, Phase = 1,
from SPI1_CLK falling		 P+4 P+5 P+6
Polarity = 1, Phase = 0,
from SPI1_CLK rising		 0.5M+P+4 0.5M+P+5 0.5M+P+6
Polarity = 1, Phase = 1,
from SPI1_CLK rising		 P+4 P+5 P+6
27 tena(SCSL_SOMI)S Delay from master asserting SPI1_SCS to slave driving SPI1_SOMI valid P+15 P+17 P+19 ns
28 tdis(SCSH_SOMI)S Delay from master deasserting SPI1_SCS to slave 3-stating SPI1_SOMI P+15 P+17 P+19 ns
(1) P = SYSCLK2 period; M = tc(SPC)M (SPI master bit clock period)
(2) Figure shows only Polarity = 0, Phase = 0 as an example. Table gives parameters for all four slave clocking modes.
(3) These parameters are in addition to the general timings for SPI slave modes (Table 6-54).

Table 6-60 Additional(4) SPI1 Slave Timings, 5-Pin Option(1)(2)

NO. PARAMETER 1.2V 1.1V 1.0V UNIT
MIN MAX MIN MAX MIN MAX
25 td(SCSL_SPC)S Required delay from SPI1_SCS asserted at slave to first SPI1_CLK edge at slave. P+1.5 P+1.5 P+1.5 ns
26 td(SPC_SCSH)S Required delay from final SPI1_CLK edge before SPI1_SCS is deasserted. Polarity = 0, Phase = 0,
from SPI1_CLK falling		 0.5M+P+4 0.5M+P+5 0.5M+P+6 ns
Polarity = 0, Phase = 1,
from SPI1_CLK falling		 P+4 P+5 P+6
Polarity = 1, Phase = 0,
from SPI1_CLK rising		 0.5M+P+4 0.5M+P+5 0.5M+P+6
Polarity = 1, Phase = 1,
from SPI1_CLK rising		 P+4 P+5 P+6
27 tena(SCSL_SOMI)S Delay from master asserting SPI1_SCS to slave driving SPI1_SOMI valid P+15 P+17 P+19 ns
28 tdis(SCSH_SOMI)S Delay from master deasserting SPI1_SCS to slave 3-stating SPI1_SOMI P+15 P+17 P+19 ns
29 tena(SCSL_ENA)S Delay from master deasserting SPI1_SCS to slave driving SPI1_ENA valid 15 17 19 ns
30 tdis(SPC_ENA)S Delay from final clock receive edge on SPI1_CLK to slave 3-stating or driving high SPI1_ENA.(3) Polarity = 0, Phase = 0,
from SPI1_CLK falling		 2.5P+15 2.5P+17 2.5P+19 ns
Polarity = 0, Phase = 1,
from SPI1_CLK rising		 2.5P+15 2.5P+17 2.5P+19
Polarity = 1, Phase = 0,
from SPI1_CLK rising		 2.5P+15 2.5P+17 2.5P+19
Polarity = 1, Phase = 1,
from SPI1_CLK falling		 2.5P+15 2.5P+17 2.5P+19
(1) P = SYSCLK2 period; M = tc(SPC)M (SPI master bit clock period)
(2) Figure shows only Polarity = 0, Phase = 0 as an example. Table gives parameters for all four slave clocking modes.
(3) SPI1_ENA is driven low after the transmission completes if the SPIINT0.ENABLE_HIGHZ bit is programmed to 0. Otherwise it is tri-stated. If tri-stated, an external pullup resistor should be used to provide a valid level to the master. This option is useful when tying several SPI slave devices to a single master.
(4) These parameters are in addition to the general timings for SPI slave modes (Table 6-54).
TMS320C6742 spitim1a_prs279.gifFigure 6-33 SPI Timings—Master Mode
TMS320C6742 spitim2_prs279.gifFigure 6-34 SPI Timings—Slave Mode
TMS320C6742 spitim3_prs279.gifFigure 6-35 SPI Timings—Master Mode (4-Pin and 5-Pin)
TMS320C6742 spitim4_prs279.gifFigure 6-36 SPI Timings—Slave Mode (4-Pin and 5-Pin)