JAJSDV7F
June 2009 – January 2017
TMS320C6742
PRODUCTION DATA.
1
デバイスの概要
1.1
特長
1.2
アプリケーション
1.3
概要
1.4
機能ブロック図
2
Revision History
3
Device Comparison
3.1
Device Characteristics
3.2
Device Compatibility
3.3
DSP Subsystem
3.3.1
C674x DSP CPU Description
3.3.2
DSP Memory Mapping
3.3.2.1
External Memories
3.3.2.2
DSP Internal Memories
3.3.2.3
C674x CPU
3.4
Memory Map Summary
Table 3-4
C6742 Top Level Memory Map
3.5
Pin Assignments
3.5.1
Pin Map (Bottom View)
3.6
Pin Multiplexing Control
3.7
Terminal Functions
3.7.1
Device Reset, NMI and JTAG
3.7.2
High-Frequency Oscillator and PLL
3.7.3
Real-Time Clock and 32-kHz Oscillator
3.7.4
DEEPSLEEP Power Control
3.7.5
External Memory Interface A (EMIFA)
3.7.6
DDR2/mDDR Controller
3.7.7
Serial Peripheral Interface Modules (SPI)
3.7.8
Enhanced Capture/Auxiliary PWM Modules (eCAP0)
3.7.9
Enhanced Pulse Width Modulators (eHRPWM)
3.7.10
Boot
3.7.11
Universal Asynchronous Receiver/Transmitters (UART0)
3.7.12
Inter-Integrated Circuit Modules(I2C0)
3.7.13
Timers
3.7.14
Multichannel Audio Serial Ports (McASP)
3.7.15
Multichannel Buffered Serial Ports (McBSP)
3.7.16
Universal Host-Port Interface (UHPI)
3.7.17
General Purpose Input Output
3.7.18
Reserved and No Connect
3.7.19
Supply and Ground
3.8
Unused Pin Configurations
4
Device Configuration
4.1
Boot Modes
4.2
SYSCFG Module
4.3
Pullup/Pulldown Resistors
5
Specifications
5.1
Absolute Maximum Ratings Over Operating Junction Temperature Range (Unless Otherwise Noted)
5.2
Handling Ratings
5.3
Recommended Operating Conditions
5.4
Notes on Recommended Power-On Hours (POH)
5.5
Electrical Characteristics Over Recommended Ranges of Supply Voltage and Operating Junction Temperature (Unless Otherwise Noted)
6
Peripheral Information and Electrical Specifications
6.1
Parameter Information
6.1.1
Parameter Information Device-Specific Information
6.1.1.1
Signal Transition Levels
6.2
Recommended Clock and Control Signal Transition Behavior
6.3
Power Supplies
6.3.1
Power-On Sequence
6.3.2
Power-Off Sequence
6.4
Reset
6.4.1
Power-On Reset (POR)
6.4.2
Warm Reset
6.4.3
Reset Electrical Data Timings
6.5
Crystal Oscillator or External Clock Input
6.6
Clock PLLs
6.6.1
PLL Device-Specific Information
6.6.2
Device Clock Generation
6.6.3
Dynamic Voltage and Frequency Scaling (DVFS)
6.7
Interrupts
6.7.1
DSP Interrupts
6.8
Power and Sleep Controller (PSC)
6.8.1
Power Domain and Module Topology
6.8.1.1
Power Domain States
6.8.1.2
Module States
6.9
Enhanced Direct Memory Access Controller (EDMA3)
6.9.1
EDMA3 Channel Synchronization Events
6.9.2
EDMA3 Peripheral Register Descriptions
6.10
External Memory Interface A (EMIFA)
6.10.1
EMIFA Asynchronous Memory Support
6.10.2
EMIFA Synchronous DRAM Memory Support
6.10.3
EMIFA SDRAM Loading Limitations
6.10.4
EMIFA Connection Examples
6.10.5
External Memory Interface Register Descriptions
6.10.6
EMIFA Electrical Data/Timing
Table 6-19
Timing Requirements for EMIFA SDRAM Interface
Table 6-20
Switching Characteristics for EMIFA SDRAM Interface
Table 6-21
Timing Requirements for EMIFA Asynchronous Memory Interface
6.11
DDR2/mDDR Memory Controller
6.11.1
DDR2/mDDR Memory Controller Electrical Data/Timing
6.11.2
DDR2/mDDR Memory Controller Register Description(s)
6.11.3
DDR2/mDDR Interface
6.11.3.1
DDR2/mDDR Interface Schematic
6.11.3.2
Compatible JEDEC DDR2/mDDR Devices
6.11.3.3
PCB Stackup
6.11.3.4
Placement
6.11.3.5
DDR2/mDDR Keep Out Region
6.11.3.6
Bulk Bypass Capacitors
6.11.3.7
High-Speed Bypass Capacitors
6.11.3.8
Net Classes
6.11.3.9
DDR2/mDDR Signal Termination
6.11.3.10
VREF Routing
6.11.3.11
DDR2/mDDR CK and ADDR_CTRL Routing
6.11.3.12
DDR2/mDDR Boundary Scan Limitations
6.12
Memory Protection Units
6.13
Multichannel Audio Serial Port (McASP)
6.13.1
McASP Peripheral Registers Description(s)
6.13.2
McASP Electrical Data/Timing
6.13.2.1
Multichannel Audio Serial Port 0 (McASP0) Timing
Table 6-42
Timing Requirements for McASP0 (1.2V, 1.1V)
Table 6-43
Timing Requirements for McASP0 (1.0V)
Table 6-44
Switching Characteristics for McASP0 (1.2V, 1.1V)
Table 6-45
Switching Characteristics for McASP0 (1.0V)
6.14
Multichannel Buffered Serial Port (McBSP)
6.14.1
McBSP Peripheral Register Description(s)
6.14.2
McBSP Electrical Data/Timing
6.14.2.1
Multichannel Buffered Serial Port (McBSP) Timing
Table 6-47
Timing Requirements for McBSP1 [1.2V, 1.1V] (see )
Table 6-48
Timing Requirements for McBSP1 [1.0V] (see )
Table 6-49
Switching Characteristics for McBSP1 [1.2V, 1.1V] (see )
Table 6-50
Switching Characteristics for McBSP1 [1.0V] (see )
Table 6-51
Timing Requirements for McBSP1 FSR When GSYNC = 1 (see )
6.15
Serial Peripheral Interface Ports (SPI1)
6.15.1
SPI Peripheral Registers Description(s)
6.15.2
SPI Electrical Data/Timing
6.15.2.1
Serial Peripheral Interface (SPI) Timing
Table 6-53
General Timing Requirements for SPI1 Master Modes
Table 6-54
General Timing Requirements for SPI1 Slave Modes
Table 6-55
Additional SPI1 Master Timings, 4-Pin Enable Option
Table 6-56
Additional SPI1 Master Timings, 4-Pin Chip Select Option
6.16
Inter-Integrated Circuit Serial Ports (I2C)
6.16.1
I2C Device-Specific Information
6.16.2
I2C Peripheral Registers Description(s)
6.16.3
I2C Electrical Data/Timing
6.16.3.1
Inter-Integrated Circuit (I2C) Timing
Table 6-62
Timing Requirements for I2C Input
Table 6-63
Switching Characteristics for I2C
6.17
Universal Asynchronous Receiver/Transmitter (UART)
6.17.1
UART Peripheral Registers Description(s)
6.17.2
UART Electrical Data/Timing
Table 6-65
Timing Requirements for UART Receive (see )
Table 6-66
Switching Characteristics Over Recommended Operating Conditions for UARTx Transmit (see )
6.18
Host-Port Interface (UHPI)
6.18.1
HPI Device-Specific Information
6.18.2
HPI Peripheral Register Description(s)
6.18.3
HPI Electrical Data/Timing
Table 6-68
Timing Requirements for Host-Port Interface [1.2V, 1.1V]
Table 6-69
Switching Characteristics Over Recommended Operating Conditions for Host-Port Interface [1.2V, 1.1V]
Table 6-70
Switching Characteristics Over Recommended Operating Conditions for Host-Port Interface [1.0V]
6.19
Enhanced Capture (eCAP) Peripheral
Table 6-72
Timing Requirements for Enhanced Capture (eCAP)
Table 6-73
Switching Characteristics Over Recommended Operating Conditions for eCAP
6.20
Enhanced High-Resolution Pulse-Width Modulator (eHRPWM)
6.20.1
Enhanced Pulse Width Modulator (eHRPWM) Timing
Table 6-75
Timing Requirements for eHRPWM
Table 6-76
Switching Characteristics Over Recommended Operating Conditions for eHRPWM
6.20.2
Trip-Zone Input Timing
6.21
Timers
6.21.1
Timer Electrical Data/Timing
Table 6-79
Timing Requirements for Timer Input (see )
Table 6-80
Switching Characteristics Over Recommended Operating Conditions for Timer Output
6.22
Real Time Clock (RTC)
6.22.1
Clock Source
6.22.2
Real-Time Clock Register Descriptions
6.23
General-Purpose Input/Output (GPIO)
6.23.1
GPIO Register Description(s)
6.23.2
GPIO Peripheral Input/Output Electrical Data/Timing
Table 6-83
Timing Requirements for GPIO Inputs (see )
Table 6-84
Switching Characteristics Over Recommended Operating Conditions for GPIO Outputs (see )
6.23.3
GPIO Peripheral External Interrupts Electrical Data/Timing
Table 6-85
Timing Requirements for External Interrupts (see )
6.24
Emulation Logic
6.24.1
JTAG Port Description
6.24.2
Scan Chain Configuration Parameters
6.24.3
Initial Scan Chain Configuration
6.24.4
IEEE 1149.1 JTAG
6.24.4.1
JTAG Peripheral Register Description(s) – JTAG ID Register (DEVIDR0)
6.24.4.2
JTAG Test-Port Electrical Data/Timing
Table 6-91
Timing Requirements for JTAG Test Port (see )
Table 6-92
Switching Characteristics Over Recommended Operating Conditions for JTAG Test Port (see )
6.24.5
JTAG 1149.1 Boundary Scan Considerations
7
Device and Documentation Support
7.1
Device Nomenclature
7.2
Tools and Software
7.3
Documentation Support
7.4
Community Resources
7.5
商標
7.6
静電気放電に関する注意事項
7.7
Export Control Notice
7.8
Glossary
8
Mechanical Packaging and Orderable Information
8.1
Thermal Data for ZCE Package
8.2
Thermal Data for ZWT Package
8.3
Packaging Information
パッケージ・オプション
デバイスごとのパッケージ図は、PDF版データシートをご参照ください。
メカニカル・データ(パッケージ|ピン)
ZWT|361
サーマルパッド・メカニカル・データ
発注情報
JAJSDV7F_pm
jajsdv7f_oa
Table 6-72
Timing Requirements for Enhanced Capture (eCAP)
TEST CONDITIONS
1.2V, 1.1V, 1.0V
UNIT
MIN
MAX
t
w(CAP)
Capture input pulse width
Asynchronous
2t
c(SCO)
cycles
Synchronous
2t
c(SCO)
cycles