JAJSDV7F June   2009  – January 2017 TMS320C6742

PRODUCTION DATA.  

  1. 1デバイスの概要
    1. 1.1 特長
    2. 1.2 アプリケーション
    3. 1.3 概要
    4. 1.4 機能ブロック図
  2. 2Revision History
  3. 3Device Comparison
    1. 3.1 Device Characteristics
    2. 3.2 Device Compatibility
    3. 3.3 DSP Subsystem
      1. 3.3.1 C674x DSP CPU Description
      2. 3.3.2 DSP Memory Mapping
        1. 3.3.2.1 External Memories
        2. 3.3.2.2 DSP Internal Memories
        3. 3.3.2.3 C674x CPU
    4. 3.4 Memory Map Summary
      1. Table 3-4 C6742 Top Level Memory Map
    5. 3.5 Pin Assignments
      1. 3.5.1 Pin Map (Bottom View)
    6. 3.6 Pin Multiplexing Control
    7. 3.7 Terminal Functions
      1. 3.7.1  Device Reset, NMI and JTAG
      2. 3.7.2  High-Frequency Oscillator and PLL
      3. 3.7.3  Real-Time Clock and 32-kHz Oscillator
      4. 3.7.4  DEEPSLEEP Power Control
      5. 3.7.5  External Memory Interface A (EMIFA)
      6. 3.7.6  DDR2/mDDR Controller
      7. 3.7.7  Serial Peripheral Interface Modules (SPI)
      8. 3.7.8  Enhanced Capture/Auxiliary PWM Modules (eCAP0)
      9. 3.7.9  Enhanced Pulse Width Modulators (eHRPWM)
      10. 3.7.10 Boot
      11. 3.7.11 Universal Asynchronous Receiver/Transmitters (UART0)
      12. 3.7.12 Inter-Integrated Circuit Modules(I2C0)
      13. 3.7.13 Timers
      14. 3.7.14 Multichannel Audio Serial Ports (McASP)
      15. 3.7.15 Multichannel Buffered Serial Ports (McBSP)
      16. 3.7.16 Universal Host-Port Interface (UHPI)
      17. 3.7.17 General Purpose Input Output
      18. 3.7.18 Reserved and No Connect
      19. 3.7.19 Supply and Ground
    8. 3.8 Unused Pin Configurations
  4. 4Device Configuration
    1. 4.1 Boot Modes
    2. 4.2 SYSCFG Module
    3. 4.3 Pullup/Pulldown Resistors
  5. 5Specifications
    1. 5.1 Absolute Maximum Ratings Over Operating Junction Temperature Range (Unless Otherwise Noted)
    2. 5.2 Handling Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Notes on Recommended Power-On Hours (POH)
    5. 5.5 Electrical Characteristics Over Recommended Ranges of Supply Voltage and Operating Junction Temperature (Unless Otherwise Noted)
  6. 6Peripheral Information and Electrical Specifications
    1. 6.1  Parameter Information
      1. 6.1.1 Parameter Information Device-Specific Information
        1. 6.1.1.1 Signal Transition Levels
    2. 6.2  Recommended Clock and Control Signal Transition Behavior
    3. 6.3  Power Supplies
      1. 6.3.1 Power-On Sequence
      2. 6.3.2 Power-Off Sequence
    4. 6.4  Reset
      1. 6.4.1 Power-On Reset (POR)
      2. 6.4.2 Warm Reset
      3. 6.4.3 Reset Electrical Data Timings
    5. 6.5  Crystal Oscillator or External Clock Input
    6. 6.6  Clock PLLs
      1. 6.6.1 PLL Device-Specific Information
      2. 6.6.2 Device Clock Generation
      3. 6.6.3 Dynamic Voltage and Frequency Scaling (DVFS)
    7. 6.7  Interrupts
      1. 6.7.1 DSP Interrupts
    8. 6.8  Power and Sleep Controller (PSC)
      1. 6.8.1 Power Domain and Module Topology
        1. 6.8.1.1 Power Domain States
        2. 6.8.1.2 Module States
    9. 6.9  Enhanced Direct Memory Access Controller (EDMA3)
      1. 6.9.1 EDMA3 Channel Synchronization Events
      2. 6.9.2 EDMA3 Peripheral Register Descriptions
    10. 6.10 External Memory Interface A (EMIFA)
      1. 6.10.1 EMIFA Asynchronous Memory Support
      2. 6.10.2 EMIFA Synchronous DRAM Memory Support
      3. 6.10.3 EMIFA SDRAM Loading Limitations
      4. 6.10.4 EMIFA Connection Examples
      5. 6.10.5 External Memory Interface Register Descriptions
      6. 6.10.6 EMIFA Electrical Data/Timing
        1. Table 6-19 Timing Requirements for EMIFA SDRAM Interface
        2. Table 6-20 Switching Characteristics for EMIFA SDRAM Interface
        3. Table 6-21 Timing Requirements for EMIFA Asynchronous Memory Interface
    11. 6.11 DDR2/mDDR Memory Controller
      1. 6.11.1 DDR2/mDDR Memory Controller Electrical Data/Timing
      2. 6.11.2 DDR2/mDDR Memory Controller Register Description(s)
      3. 6.11.3 DDR2/mDDR Interface
        1. 6.11.3.1  DDR2/mDDR Interface Schematic
        2. 6.11.3.2  Compatible JEDEC DDR2/mDDR Devices
        3. 6.11.3.3  PCB Stackup
        4. 6.11.3.4  Placement
        5. 6.11.3.5  DDR2/mDDR Keep Out Region
        6. 6.11.3.6  Bulk Bypass Capacitors
        7. 6.11.3.7  High-Speed Bypass Capacitors
        8. 6.11.3.8  Net Classes
        9. 6.11.3.9  DDR2/mDDR Signal Termination
        10. 6.11.3.10 VREF Routing
        11. 6.11.3.11 DDR2/mDDR CK and ADDR_CTRL Routing
        12. 6.11.3.12 DDR2/mDDR Boundary Scan Limitations
    12. 6.12 Memory Protection Units
    13. 6.13 Multichannel Audio Serial Port (McASP)
      1. 6.13.1 McASP Peripheral Registers Description(s)
      2. 6.13.2 McASP Electrical Data/Timing
        1. 6.13.2.1 Multichannel Audio Serial Port 0 (McASP0) Timing
          1. Table 6-42 Timing Requirements for McASP0 (1.2V, 1.1V)
          2. Table 6-43 Timing Requirements for McASP0 (1.0V)
          3. Table 6-44 Switching Characteristics for McASP0 (1.2V, 1.1V)
          4. Table 6-45 Switching Characteristics for McASP0 (1.0V)
    14. 6.14 Multichannel Buffered Serial Port (McBSP)
      1. 6.14.1 McBSP Peripheral Register Description(s)
      2. 6.14.2 McBSP Electrical Data/Timing
        1. 6.14.2.1 Multichannel Buffered Serial Port (McBSP) Timing
          1. Table 6-47 Timing Requirements for McBSP1 [1.2V, 1.1V] (see )
          2. Table 6-48 Timing Requirements for McBSP1 [1.0V] (see )
          3. Table 6-49 Switching Characteristics for McBSP1 [1.2V, 1.1V] (see )
          4. Table 6-50 Switching Characteristics for McBSP1 [1.0V] (see )
          5. Table 6-51 Timing Requirements for McBSP1 FSR When GSYNC = 1 (see )
    15. 6.15 Serial Peripheral Interface Ports (SPI1)
      1. 6.15.1 SPI Peripheral Registers Description(s)
      2. 6.15.2 SPI Electrical Data/Timing
        1. 6.15.2.1 Serial Peripheral Interface (SPI) Timing
          1. Table 6-53 General Timing Requirements for SPI1 Master Modes
          2. Table 6-54 General Timing Requirements for SPI1 Slave Modes
          3. Table 6-55 Additional SPI1 Master Timings, 4-Pin Enable Option
          4. Table 6-56 Additional SPI1 Master Timings, 4-Pin Chip Select Option
    16. 6.16 Inter-Integrated Circuit Serial Ports (I2C)
      1. 6.16.1 I2C Device-Specific Information
      2. 6.16.2 I2C Peripheral Registers Description(s)
      3. 6.16.3 I2C Electrical Data/Timing
        1. 6.16.3.1 Inter-Integrated Circuit (I2C) Timing
          1. Table 6-62 Timing Requirements for I2C Input
          2. Table 6-63 Switching Characteristics for I2C
    17. 6.17 Universal Asynchronous Receiver/Transmitter (UART)
      1. 6.17.1 UART Peripheral Registers Description(s)
      2. 6.17.2 UART Electrical Data/Timing
        1. Table 6-65 Timing Requirements for UART Receive (see )
        2. Table 6-66 Switching Characteristics Over Recommended Operating Conditions for UARTx Transmit (see )
    18. 6.18 Host-Port Interface (UHPI)
      1. 6.18.1 HPI Device-Specific Information
      2. 6.18.2 HPI Peripheral Register Description(s)
      3. 6.18.3 HPI Electrical Data/Timing
        1. Table 6-68 Timing Requirements for Host-Port Interface [1.2V, 1.1V]
        2. Table 6-69 Switching Characteristics Over Recommended Operating Conditions for Host-Port Interface [1.2V, 1.1V]
        3. Table 6-70 Switching Characteristics Over Recommended Operating Conditions for Host-Port Interface [1.0V]
    19. 6.19 Enhanced Capture (eCAP) Peripheral
      1. Table 6-72 Timing Requirements for Enhanced Capture (eCAP)
      2. Table 6-73 Switching Characteristics Over Recommended Operating Conditions for eCAP
    20. 6.20 Enhanced High-Resolution Pulse-Width Modulator (eHRPWM)
      1. 6.20.1 Enhanced Pulse Width Modulator (eHRPWM) Timing
        1. Table 6-75 Timing Requirements for eHRPWM
        2. Table 6-76 Switching Characteristics Over Recommended Operating Conditions for eHRPWM
      2. 6.20.2 Trip-Zone Input Timing
    21. 6.21 Timers
      1. 6.21.1 Timer Electrical Data/Timing
        1. Table 6-79 Timing Requirements for Timer Input (see )
        2. Table 6-80 Switching Characteristics Over Recommended Operating Conditions for Timer Output
    22. 6.22 Real Time Clock (RTC)
      1. 6.22.1 Clock Source
      2. 6.22.2 Real-Time Clock Register Descriptions
    23. 6.23 General-Purpose Input/Output (GPIO)
      1. 6.23.1 GPIO Register Description(s)
      2. 6.23.2 GPIO Peripheral Input/Output Electrical Data/Timing
        1. Table 6-83 Timing Requirements for GPIO Inputs (see )
        2. Table 6-84 Switching Characteristics Over Recommended Operating Conditions for GPIO Outputs (see )
      3. 6.23.3 GPIO Peripheral External Interrupts Electrical Data/Timing
        1. Table 6-85 Timing Requirements for External Interrupts (see )
    24. 6.24 Emulation Logic
      1. 6.24.1 JTAG Port Description
      2. 6.24.2 Scan Chain Configuration Parameters
      3. 6.24.3 Initial Scan Chain Configuration
      4. 6.24.4 IEEE 1149.1 JTAG
        1. 6.24.4.1 JTAG Peripheral Register Description(s) – JTAG ID Register (DEVIDR0)
        2. 6.24.4.2 JTAG Test-Port Electrical Data/Timing
          1. Table 6-91 Timing Requirements for JTAG Test Port (see )
          2. Table 6-92 Switching Characteristics Over Recommended Operating Conditions for JTAG Test Port (see )
      5. 6.24.5 JTAG 1149.1 Boundary Scan Considerations
  7. 7Device and Documentation Support
    1. 7.1 Device Nomenclature
    2. 7.2 Tools and Software
    3. 7.3 Documentation Support
    4. 7.4 Community Resources
    5. 7.5 商標
    6. 7.6 静電気放電に関する注意事項
    7. 7.7 Export Control Notice
    8. 7.8 Glossary
  8. 8Mechanical Packaging and Orderable Information
    1. 8.1 Thermal Data for ZCE Package
    2. 8.2 Thermal Data for ZWT Package
    3. 8.3 Packaging Information

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • ZWT|361
サーマルパッド・メカニカル・データ
発注情報

6.7.1 DSP Interrupts

The C674x DSP interrupt controller combines device events into 12 prioritized interrupts. The source for each of the 12 CPU interrupts is user programmable and is listed in Table 6-6. Also, the interrupt controller controls the generation of the CPU exceptions, NMI, and emulation interrupts. Table 6-7 summarizes the C674x interrupt controller registers and memory locations.

Refer to the C674x DSP MegaModule Reference Guide (SPRUFK5) and the TMS320C674x DSP CPU and Instruction Set Reference Guide (SPRUFE8) for details of the C674x interrupts.

Table 6-6 C6742 DSP Interrupts

EVT# Interrupt Name Source
0 EVT0 C674x Int Ctl 0
1 EVT1 C674x Int Ctl 1
2 EVT2 C674x Int Ctl 2
3 EVT3 C674x Int Ctl 3
4 T64P0_TINT12 Timer64P0 - TINT12
5 SYSCFG_CHIPINT2 SYSCFG CHIPSIG Register
6 - Reserved
7 EHRPWM0 HiResTimer/PWM0 Interrupt
8 EDMA3_0_CC0_INT1 EDMA3_0 Channel Controller 0 Shadow Region 1 Transfer Completion Interrupt
9 EMU_DTDMA C674x-ECM
10 EHRPWM0TZ HiResTimer/PWM0 Trip Zone Interrupt
11 EMU_RTDXRX C674x-RTDX
12 EMU_RTDXTX C674x-RTDX
13 IDMAINT0 C674x-EMC
14 IDMAINT1 C674x-EMC
15-17 - Reserved
18 EHRPWM1 HiResTimer/PWM1 Interrupt
19-22 - Reserved
22 - Reserved
23 EHRPWM1TZ HiResTimer/PWM1 Trip Zone Interrupt
24-33 - Reserved
34 UHPI_DSPINT UHPI DSP Interrupt
35 - Reserved
36 IIC0_INT I2C0
37 - Reserved
38 UART0_INT UART0
39 - Reserved
40 T64P1_TINT12 Timer64P1 Interrupt 12
41 GPIO_B1INT GPIO Bank 1 Interrupt
42 - Reserved
43 SPI1_INT SPI1
44 - Reserved
45 ECAP0 ECAP0
46 - Reserved
47 ECAP1 ECAP1
48 T64P1_TINT34 Timer64P1 Interrupt 34
49 GPIO_B2INT GPIO Bank 2 Interrupt
50 - Reserved
51 ECAP2 ECAP2
52 GPIO_B3INT GPIO Bank 3 Interrupt
53 - Reserved
54 GPIO_B4INT GPIO Bank 4 Interrupt
55 EMIFA_INT EMIFA
56 EDMA3_0_CC0_ERRINT EDMA3_0 Channel Controller 0 Error Interrupt
57 EDMA3_0_TC0_ERRINT EDMA3_0 Transfer Controller 0 Error Interrupt
58 EDMA3_0_TC1_ERRINT EDMA3_0 Transfer Controller 1 Error Interrupt
59 GPIO_B5INT GPIO Bank 5 Interrupt
60 DDR2_MEMERR DDR2 Memory Error Interrupt
61 MCASP0_INT McASP0 Combined RX/TX Interrupts
62 GPIO_B6INT GPIO Bank 6 Interrupt
63 RTC_IRQS RTC Combined
64 T64P0_TINT34 Timer64P0 Interrupt 34
65 GPIO_B0INT GPIO Bank 0 Interrupt
66 - Reserved
67 SYSCFG_CHIPINT3 SYSCFG_CHIPSIG Register
68 - Reserved
69 - Reserved
70 PSC0_ALLINT PSC0
71 PSC1_ALLINT PSC1
72 GPIO_B7INT GPIO Bank 7 Interrupt
73 - Reserved
74 PROTERR SYSCFG Protection Shared Interrupt
75 GPIO_B8INT GPIO Bank 8 Interrupt
76-88 - Reserved
89 MCBSP1_RINT McBSP1 Receive Interrupt
90 MCBSP1_XINT McBSP1 Transmit Interrupt
91 EDMA3_1_CC0_INT1 EDMA3_1 Channel Controller 0 Shadow Region 1 Transfer Completion Interrupt
92 EDMA3_1_CC0_ERRINT EDMA3_1 Channel Controller 0 Error Interrupt
93 EDMA3_1_TC0_ERRINT EDMA3_1 Transfer Controller 0 Error Interrupt
94-95 - Reserved
96 INTERR C674x-Int Ctl
97 EMC_IDMAERR C674x-EMC
98 - 112 - Reserved
113 PMC_ED C674x-PMC
114 - 115 - Reserved
116 UMC_ED1 C674x-UMC
117 UMC_ED2 C674x-UMC
118 PDC_INT C674x-PDC
119 SYS_CMPA C674x-SYS
120 PMC_CMPA C674x-PMC
121 PMC_CMPA C674x-PMC
122 DMC_CMPA C674x-DMC
123 DMC_CMPA C674x-DMC
124 UMC_CMPA C674x-UMC
125 UMC_CMPA C674x-UMC
126 EMC_CMPA C674x-EMC
127 EMC_BUSERR C674x-EMC

Table 6-7 C674x DSP Interrupt Controller Registers

BYTE ADDRESS ACRONYM DESCRIPTION
0x0180 0000 EVTFLAG0 Event flag register 0
0x0180 0004 EVTFLAG1 Event flag register 1
0x0180 0008 EVTFLAG2 Event flag register 2
0x0180 000C EVTFLAG3 Event flag register 3
0x0180 0020 EVTSET0 Event set register 0
0x0180 0024 EVTSET1 Event set register 1
0x0180 0028 EVTSET2 Event set register 2
0x0180 002C EVTSET3 Event set register 3
0x0180 0040 EVTCLR0 Event clear register 0
0x0180 0044 EVTCLR1 Event clear register 1
0x0180 0048 EVTCLR2 Event clear register 2
0x0180 004C EVTCLR3 Event clear register 3
0x0180 0080 EVTMASK0 Event mask register 0
0x0180 0084 EVTMASK1 Event mask register 1
0x0180 0088 EVTMASK2 Event mask register 2
0x0180 008C EVTMASK3 Event mask register 3
0x0180 00A0 MEVTFLAG0 Masked event flag register 0
0x0180 00A4 MEVTFLAG1 Masked event flag register 1
0x0180 00A8 MEVTFLAG2 Masked event flag register 2
0x0180 00AC MEVTFLAG3 Masked event flag register 3
0x0180 00C0 EXPMASK0 Exception mask register 0
0x0180 00C4 EXPMASK1 Exception mask register 1
0x0180 00C8 EXPMASK2 Exception mask register 2
0x0180 00CC EXPMASK3 Exception mask register 3
0x0180 00E0 MEXPFLAG0 Masked exception flag register 0
0x0180 00E4 MEXPFLAG1 Masked exception flag register 1
0x0180 00E8 MEXPFLAG2 Masked exception flag register 2
0x0180 00EC MEXPFLAG3 Masked exception flag register 3
0x0180 0104 INTMUX1 Interrupt mux register 1
0x0180 0108 INTMUX2 Interrupt mux register 2
0x0180 010C INTMUX3 Interrupt mux register 3
0x0180 0140 - 0x0180 0144 - Reserved
0x0180 0180 INTXSTAT Interrupt exception status
0x0180 0184 INTXCLR Interrupt exception clear
0x0180 0188 INTDMASK Dropped interrupt mask register
0x0180 01C0 EVTASRT Event assert register